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Searched full:ls1 (Results 1 – 13 of 13) sorted by relevance

/freebsd/crypto/libecc/src/utils/
H A Dutils.c100 const char *ls1 = s1, *ls2 = s2; in are_str_equal() local
105 while (*ls1 && (*ls1 == *ls2)) { in are_str_equal()
106 ls1++; in are_str_equal()
110 (*check) = (*ls1 == *ls2); in are_str_equal()
125 const char *ls1 = s1, *ls2 = s2; in are_str_equal_nlen() local
131 while (*ls1 && (*ls1 == *ls2) && (i < maxlen)) { in are_str_equal_nlen()
132 ls1++; in are_str_equal_nlen()
137 (*check) = (*ls1 == *ls2); in are_str_equal_nlen()
/freebsd/contrib/llvm-project/llvm/lib/Target/Hexagon/
H A DHexagonConstPropagation.cpp1108 LatticeCell LS1, LS2; in evaluateCMPrr() local
1109 if (!getCell(R1, Inputs, LS1) || !getCell(R2, Inputs, LS2)) in evaluateCMPrr()
1112 bool IsProp1 = LS1.isProperty(); in evaluateCMPrr()
1115 uint32_t Prop1 = LS1.properties(); in evaluateCMPrr()
1412 LatticeCell LS1; in evaluateANDri() local
1413 if (!getCell(R1, Inputs, LS1)) in evaluateANDri()
1415 if (LS1.isBottom() || LS1.isProperty()) in evaluateANDri()
1419 for (unsigned i = 0; i < LS1.size(); ++i) { in evaluateANDri()
1420 bool Eval = constToInt(LS1 in evaluateANDri()
1479 LatticeCell LS1; evaluateORri() local
1506 LatticeCell LS1, LS2; evaluateXORrr() local
1535 LatticeCell LS1; evaluateXORri() local
1568 LatticeCell LS1; evaluateZEXTr() local
1599 LatticeCell LS1; evaluateSEXTr() local
1664 LatticeCell LS1; evaluateCLBr() local
1699 LatticeCell LS1; evaluateCTBr() local
1736 LatticeCell LS1; evaluateEXTRACTr() local
1793 LatticeCell LS1; evaluateSplatr() local
3041 LatticeCell LS1, LS2; rewriteHexConstUses() local
3077 LatticeCell LS1, LS2; rewriteHexConstUses() local
[all...]
/freebsd/contrib/llvm-project/llvm/lib/Target/AArch64/
H A DAArch64SchedThunderX3T110.td291 // 1 cycle on LS0/LS1.
297 // 2 cycles on LS0/LS1.
303 // 4 cycles on LS0/LS1.
310 // 5 cycles on LS0/LS1.
316 // 6 cycles on LS0/LS1.
322 // 4 + 5 cycles on LS0/LS1.
332 // 4 + 8 cycles on LS0/LS1.
342 // 11 cycles on LS0/LS1 and I1.
349 // 1 cycles on LS0/LS1 and I0/I1/I2/I3.
356 // 1 cycles on LS0/LS1 an
[all...]
H A DAArch64SchedThunderX2T99.td213 // 1 cycles on LS0 or LS1.
218 // 1 cycles on LS0 or LS1 and I0, I1, or I2.
224 // 1 cycles on LS0 or LS1 and 2 of I0, I1, or I2.
231 // 2 cycles on LS0 or LS1.
237 // 4 cycles on LS0 or LS1.
243 // 5 cycles on LS0 or LS1.
249 // 6 cycles on LS0 or LS1.
255 // 4 cycles on LS0 or LS1 and I0, I1, or I2.
261 // 4 cycles on LS0 or LS1 and 2 of I0, I1, or I2.
268 // 5 cycles on LS0 or LS1 an
[all...]
H A DAArch64SchedOryon.td79 // Port 7: Load/store. LS1
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A Dother.json317 … "Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data fini…
659 …located through the hardware prefetch mechanism or through software. This is combined ls0 and ls1",
1637 "BriefDescription": "LS1 ISU reject",
2417 "BriefDescription": "LS1 L1 D cache load references counted at finish, gated by reject",
2418 …"PublicDescription": "LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D c…
2465 "BriefDescription": "LS1 Erat miss due to prefetch",
2466 "PublicDescription": "LS1 Erat miss due to prefetch42"
2471 "BriefDescription": "LS1 L1 cache data prefetches",
2472 "PublicDescription": "LS1 L1 cache data prefetches42"
2573 "BriefDescription": "LS1 Flush: LRQ",
[all …]
/freebsd/sys/contrib/device-tree/Bindings/pwm/
H A Dpwm-fsl-ftm.txt11 LS1 | BE
H A Dfsl,vf610-ftm-pwm.yaml18 LS1 | BE
/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A Dother.json535 "BriefDescription": "LS1 finished load vector op"
695 "BriefDescription": "LS1 Erat miss due to prefetch"
1655 "BriefDescription": "ls1 l1 tm cam cancel"
1665 "BriefDescription": "LS1 Erat miss due to prefetch"
2310 …st. No record of issue pipe (LS0/LS1) is maintained so this is for both pipes. Probably don't need…
/freebsd/lib/libiconv_modules/ISO2022/
H A Dcitrus_iso2022.c333 { "LS1", F_LS1 }, in get_flags()
517 /* LS1/2/3R */
665 /* LS1/2/3R */ in _ISO2022_sgetwchar()
/freebsd/contrib/llvm-project/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp2824 GLoadStore *LS1 = dyn_cast<GLoadStore>(I1); in matchEqualDefs() local
2826 if (!LS1 || !LS2) in matchEqualDefs()
2830 (LS1->getMemSizeInBits() != LS2->getMemSizeInBits())) in matchEqualDefs()
/freebsd/share/misc/
H A Dusb_vendors2984 c062 M-UAS144 [LS1 Laser Mouse]
/freebsd/contrib/ncurses/misc/
H A Dterminfo.src24668 # (Q) SI is also called LS1, Locking Shift One.