Lines Matching full:ls1
317 … "Completion stall by stores this includes store agen finishes in pipe LS0/LS1 and store data fini…
659 …located through the hardware prefetch mechanism or through software. This is combined ls0 and ls1",
1637 "BriefDescription": "LS1 ISU reject",
2417 "BriefDescription": "LS1 L1 D cache load references counted at finish, gated by reject",
2418 …"PublicDescription": "LS1 L1 D cache load references counted at finish, gated by rejectLSU1 L1 D c…
2465 "BriefDescription": "LS1 Erat miss due to prefetch",
2466 "PublicDescription": "LS1 Erat miss due to prefetch42"
2471 "BriefDescription": "LS1 L1 cache data prefetches",
2472 "PublicDescription": "LS1 L1 cache data prefetches42"
2573 "BriefDescription": "LS1 Flush: LRQ",
2574 "PublicDescription": "LS1 Flush: LRQLSU1 LRQ flushes"
2579 "BriefDescription": "LS1 Flush: SRQ",
2580 "PublicDescription": "LS1 Flush: SRQLSU1 SRQ lhs flushes"
2591 "BriefDescription": "LS1 Flush: Unaligned Store",
2592 "PublicDescription": "LS1 Flush: Unaligned StoreLSU1 unaligned store flushes"
2597 "BriefDescription": "ls1 l1 tm cam cancel",
2598 "PublicDescription": "ls1 l1 tm cam cancel42"
2609 "BriefDescription": "LS1 Load Merge with another cacheline request",
2610 "PublicDescription": "LS1 Load Merge with another cacheline request42"
2615 "BriefDescription": "LS1 Non-cachable Loads counted at finish",
2616 "PublicDescription": "LS1 Non-cachable Loads counted at finishLSU1 non-cacheable loads"
2633 "BriefDescription": "LS1 SRQ forwarded data to a load",
2634 "PublicDescription": "LS1 SRQ forwarded data to a loadLSU1 SRQ store forwarded"
2639 "BriefDescription": "ls1 store reject",
2640 "PublicDescription": "ls1 store reject42"
2783 "BriefDescription": "LS1 Vector Loads",
2784 "PublicDescription": "LS1 Vector Loads42"
2789 "BriefDescription": "LS1 Load Merge with another cacheline request",
2790 "PublicDescription": "LS1 Load Merge with another cacheline request42"
2933 "BriefDescription": "count at finish so can return only on ls0 or ls1",