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/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr-channel.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
7 title: LPDDR channel with chip/rank topology description
10 An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
11 CK, etc.) that connect one or more LPDDR chips to a host system. The main
12 purpose of this node is to overall LPDDR topology of the system, including the
13 amount of individual LPDDR chips and the ranks per chip.
29 from (a multiple of) the io-width of the LPDDR chip, that means that
35 connected LPDDR chip, times the io-width of the channel divided by
36 the io-width of the LPDDR chip.
54 Each physical LPDDR chip may have one or more ranks. Ranks are
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H A Djedec,lpddr-props.yaml4 $id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
7 title: Common properties for LPDDR types
10 Different LPDDR types generally use the same properties and only differ in the
13 an LPDDR channel node.
23 lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
26 The latter form can be useful when LPDDR nodes are created at runtime by
31 The rank number of this LPDDR rank when used as a subnode to an LPDDR
H A Djedec,lpddr4.yaml13 - $ref: jedec,lpddr-props.yaml#
30 lpddr {
H A Djedec,lpddr5.yaml13 - $ref: jedec,lpddr-props.yaml#
40 lpddr {
H A Djedec,lpddr2.yaml13 - $ref: jedec,lpddr-props.yaml#
H A Djedec,lpddr3.yaml13 - $ref: jedec,lpddr-props.yaml#
/linux/drivers/mtd/lpddr/
H A DKconfig2 menu "LPDDR & LPDDR2 PCM memory drivers"
6 tristate "Support for LPDDR flash chips"
9 This option enables support of LPDDR (Low power double data rate)
17 Device Information for LPDDR chips is offered through the Overlay
H A DMakefile3 # linux/drivers/mtd/lpddr/Makefile
/linux/include/linux/mtd/
H A Dpfow.h3 * and service functions used by LPDDR chips
19 /* Identification info for LPDDR chip */
47 /* LPDDR memory device command codes */
H A Dqinfo.h13 /* lpddr_private describes lpddr flash chip in memory map
/linux/drivers/mtd/
H A DMakefile29 obj-y += chips/ lpddr/ maps/ devices/ nand/ tests/
H A DKconfig217 source "drivers/mtd/lpddr/Kconfig"
/linux/arch/arm64/boot/dts/allwinner/
H A Dsun50i-a64-sopine.dtsi114 regulator-name = "vdd-1v8-lpddr";
/linux/arch/arm64/boot/dts/qcom/
H A Dmsm8916-pm8916.dtsi98 regulator-always-on; /* Needed for LPDDR RAM */
H A Dmsm8939-pm8916.dtsi76 regulator-always-on; /* Needed for LPDDR RAM */
H A Dmsm8929-pm8916.dtsi76 regulator-always-on; /* Needed for LPDDR RAM */
/linux/include/soc/at91/
H A Dat91sam9_ddrsdr.h80 #define AT91_DDRSDRC_LPDDR2_PWOFF (1 << 3) /* LPDDR Power Off */
/linux/drivers/acpi/pmic/
H A Dintel_pmic_bytcrc.c104 }, /* V18U -> V1P8U, LPDDR */
/linux/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Dclk_mgr.h244 * we have 2 DPM and LPDDR, we will WM set A, B and
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8mn-beacon-som.dtsi47 /* DDR controller is running LPDDR at 800MHz which requires 0.95V */
/linux/drivers/i2c/
H A Di2c-smbus.c430 case 0x1B: /* LPDDR */ in i2c_register_spd()
/linux/arch/arm64/boot/dts/rockchip/
H A Drk3399-gru.dtsi52 pp1200_lpddr: regulator-pp1200-lpddr {
/linux/drivers/memory/tegra/
H A Dtegra20-emc.c575 /* these registers are standard for all LPDDR JEDEC memory chips */ in emc_read_lpddr_sdram_info()
H A Dtegra30-emc.c1100 /* these registers are standard for all LPDDR JEDEC memory chips */ in emc_read_lpddr_sdram_info()