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/linux/tools/perf/pmu-events/arch/arm64/hisilicon/hip08/
H A Duncore-l3c.json6 "Unit": "hisi_sccl,l3c"
12 "Unit": "hisi_sccl,l3c"
18 "Unit": "hisi_sccl,l3c"
24 "Unit": "hisi_sccl,l3c"
29 "BriefDescription": "l3c precharge commands",
30 "Unit": "hisi_sccl,l3c"
36 "Unit": "hisi_sccl,l3c"
42 "Unit": "hisi_sccl,l3c"
47 "BriefDescription": "Count of the number of read lines that hits in spipe of this L3C",
48 "Unit": "hisi_sccl,l3c"
[all …]
/linux/Documentation/admin-guide/perf/
H A Dhisi-pmu.rst6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
19 interrupt, and the PMU driver shall register perf PMU drivers like L3C,
23 /sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>
27 Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU
32 e.g. hisi_sccl3_l3c0/rd_hit_cpipe is READ_HIT_CPIPE event of L3C index #0 in
62 1. L3C PMU supports filtering by core/thread within the cluster which can be
71 which may not cover all the core/thread sharing L3C.
86 - 5'b00001: comes from L3C in this die;
87 - 5'b01000: comes from L3C in the cross-die;
88 - 5'b01001: comes from L3C which is in another socket;
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H A Dthunderx2-pmu.rst6 PMUs such as the Level 3 Cache (L3C), DDR4 Memory Controller (DMC) and
9 The DMC has 8 interleaved channels and the L3C has 16 interleaved tiles.
13 The DMC and L3C support up to 4 counters, while the CCPI2 supports up to 8
16 overflow interrupt. DMC and L3C counters are 32-bit and read every 2 seconds.
22 L3C devices. Each PMU can be used to count up to 4 (DMC/L3C) or up to 8
H A Dxgene-pmu.rst39 / # perf list | grep -e l3c -e iob -e mcb -e mc
/linux/drivers/perf/hisilicon/
H A Dhisi_uncore_l3c_pmu.c3 * HiSilicon SoC L3C uncore Hardware event counters support
21 /* L3C register definition */
40 /* L3C has 8-counters */
127 * For an L3C PMU that supports extension events, we can monitor in hisi_l3c_pmu_get_event_idx()
544 * Use the SCCL_ID and CCL_ID to identify the L3C PMU, while in hisi_l3c_pmu_init_data()
548 dev_err(&pdev->dev, "Can not read l3c sccl-id!\n"); in hisi_l3c_pmu_init_data()
553 dev_err(&pdev->dev, "Can not read l3c ccl-id!\n"); in hisi_l3c_pmu_init_data()
578 /* HiSilicon L3C PMU supporting ext should have more than 1 irq resources. */ in hisi_l3c_pmu_init_ext()
859 dev_err(l3c_pmu->dev, "L3C PMU register failed!\n"); in hisi_l3c_pmu_probe()
904 /* Avoid L3C pmu not supporting ext from ext irq migrating. */ in hisi_l3c_pmu_online_cpu()
[all …]
H A Dhisi_uncore_hha_pmu.c171 /* Read 64 bits and like L3C, top 16 bits are RAZ */ in hisi_hha_pmu_read_counter()
178 /* Write 64 bits and like L3C, top 16 bits are WI */ in hisi_hha_pmu_write_counter()
/linux/tools/perf/pmu-events/arch/test/test_soc/cpu/
H A Duncore.json42 "Unit": "hisi_sccl,l3c"
/linux/drivers/perf/
H A DKconfig217 The SoC has PMU support in its L3 cache controller (L3C) and
/linux/Documentation/admin-guide/laptops/
H A Dasus-laptop.rst177 Note: on some machines (e.g. L3C), after the module has been loaded, only 0x6n
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra194.dtsi3049 next-level-cache = <&l3c>;
3059 next-level-cache = <&l3c>;
3069 next-level-cache = <&l3c>;
3079 next-level-cache = <&l3c>;
3082 l3c: l3-cache { label
/linux/tools/perf/pmu-events/
H A Dempty-pmu-events.c64 /* offset=3628 */ "hisi_sccl,l3c\000"
180 .pmu_name = { 3628 /* hisi_sccl,l3c\000 */ },
H A Djevents.py289 'hisi_sccl,l3c': 'hisi_sccl,l3c',
/linux/tools/perf/tests/
H A Dpmu-events.c179 .pmu = "hisi_sccl,l3c",
/linux/drivers/platform/mellanox/
H A Dmlxbf-pmc.c1720 /* Do not allow writes to the L3C regs */ in mlxbf_pmc_counter_store()
1998 /* "enable" sysfs to start/stop the counters. Only in L3C blocks */ in mlxbf_pmc_init_perftype_counter()
/linux/drivers/pci/
H A Dquirks.c1523 case 0x1626: /* L3C notebook */ in asus_hides_smbus_hostbridge()