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/linux/drivers/pci/pcie/
H A Daspm.c3 * Enable PCIe link L0s/L1 state and Clock Power Management
100 * Save L1 substate configuration. The ASPM L0s/L1 configuration in pci_save_aspm_l1ss_state()
155 /* Make sure L0s/L1 are disabled before updating L1SS config */ in pci_restore_aspm_l1ss_state()
199 /* Restore L0s/L1 if they were enabled */ in pci_restore_aspm_l1ss_state()
215 #define PCIE_LINK_STATE_L0S_UP BIT(0) /* Upstream direction L0s state */
216 #define PCIE_LINK_STATE_L0S_DW BIT(1) /* Downstream direction L0s state */
296 /* Enable ASPM L0s/L1 */ in policy_to_aspm_state()
475 /* Convert L0s latency encoding to ns */
485 /* Convert L0s acceptable latency encoding to ns */
581 /* Calculate endpoint L0s acceptable latency */ in pcie_aspm_check_latency()
[all …]
/linux/Documentation/devicetree/bindings/pci/
H A Dnvidia,tegra194-pcie-ep.yaml159 nvidia,aspm-l0s-entrance-latency-us:
160 description: ASPM L0s entrance latency to be specified in microseconds
244 nvidia,aspm-l0s-entrance-latency-us = <3>;
300 nvidia,aspm-l0s-entrance-latency-us = <3>;
H A Dbrcm,stb-pcie.yaml67 aspm-no-l0s: true
75 Power Management, L0s, and L1, but cannot provide L1 substate (L1SS)
78 potentially hanging the system; "default" -- which provides L0s, L1,
H A Dnvidia,tegra194-pcie.yaml174 nvidia,aspm-l0s-entrance-latency-us:
175 description: ASPM L0s entrance latency to be specified in microseconds
303 nvidia,aspm-l0s-entrance-latency-us = <3>;
367 nvidia,aspm-l0s-entrance-latency-us = <3>;
/linux/drivers/net/wireless/mediatek/mt76/
H A Dpci.c28 (aspm_conf & PCI_EXP_LNKCTL_ASPM_L0S) ? "L0s" : "", in mt76_pci_disable_aspm()
/linux/drivers/net/wireless/intel/iwlwifi/pcie/
H A Dtrans-gen2.c32 * Disable L0s without affecting L1; in iwl_pcie_gen2_apm_init()
33 * don't wait for ICH L0s (ICH bug W/A) in iwl_pcie_gen2_apm_init()
43 * wake device's PCI Express link L1a -> L0s in iwl_pcie_gen2_apm_init()
H A Dtrans.c263 * L0S states have been found to be unstable with our devices in iwl_pcie_apm_config()
295 /* Disable L0S exit timer (platform NMI Work/Around) */ in iwl_pcie_apm_init()
301 * Disable L0s without affecting L1; in iwl_pcie_apm_init()
302 * don't wait for ICH L0s (ICH bug W/A) in iwl_pcie_apm_init()
312 * wake device's PCI Express link L1a -> L0s in iwl_pcie_apm_init()
/linux/drivers/char/xillybus/
H A Dxillybus_pcie.c57 /* L0s has caused packet drops. No power saving, thank you. */ in xilly_probe()
/linux/drivers/pci/controller/
H A Dpcie-rockchip-host.c303 /* Fix the transmitted FTS count desired to exit from L0s. */ in rockchip_pcie_host_init_port()
381 /* Clear L0s from RC's link cap */ in rockchip_pcie_host_init_port()
382 if (of_property_read_bool(dev->of_node, "aspm-no-l0s")) { in rockchip_pcie_host_init_port()
H A Dpcie-brcmstb.c1174 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
1176 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1276 * "no-l1ss" -- Provides Clock Power Management, L0s, and in brcm_config_clkreq()
1295 * "default" -- Provides L0s, L1, and L1SS, but not in brcm_config_clkreq()
/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra234.dtsi4489 nvidia,aspm-l0s-entrance-latency-us = <3>;
4543 nvidia,aspm-l0s-entrance-latency-us = <3>;
4597 nvidia,aspm-l0s-entrance-latency-us = <3>;
4641 nvidia,aspm-l0s-entrance-latency-us = <3>;
4689 nvidia,aspm-l0s-entrance-latency-us = <3>;
4743 nvidia,aspm-l0s-entrance-latency-us = <3>;
4797 nvidia,aspm-l0s-entrance-latency-us = <3>;
4851 nvidia,aspm-l0s-entrance-latency-us = <3>;
4890 nvidia,aspm-l0s-entrance-latency-us = <3>;
4936 nvidia,aspm-l0s-entrance-latency-us = <3>;
[all …]
H A Dtegra194.dtsi2397 nvidia,aspm-l0s-entrance-latency-us = <3>;
2449 nvidia,aspm-l0s-entrance-latency-us = <3>;
2501 nvidia,aspm-l0s-entrance-latency-us = <3>;
2553 nvidia,aspm-l0s-entrance-latency-us = <3>;
2598 nvidia,aspm-l0s-entrance-latency-us = <3>;
2644 nvidia,aspm-l0s-entrance-latency-us = <3>;
2689 nvidia,aspm-l0s-entrance-latency-us = <3>;
2738 nvidia,aspm-l0s-entrance-latency-us = <3>;
2786 nvidia,aspm-l0s-entrance-latency-us = <3>;
/linux/drivers/net/ethernet/atheros/alx/
H A Dreg.h84 /* bit30: L0s/L1 controlled by MAC based on throughput(setting in 15A0) */
90 /* bit[23:20] if pm_request_l1 time > @, then enter L0s not L1 */
H A Dhw.c424 /* dis l0s/l1 before mac reset */ in alx_reset_mac()
458 /* restore l0s / l1 */ in alx_reset_mac()
/linux/drivers/pci/controller/dwc/
H A Dpcie-tegra194.c653 seq_printf(s, "Tx L0s entry count : %u\n", in aspm_state_cnt()
656 seq_printf(s, "Rx L0s entry count : %u\n", in aspm_state_cnt()
706 /* Program L0s and L1 entrance latencies */ in init_host_aspm()
1125 ret = of_property_read_u32(np, "nvidia,aspm-l0s-entrance-latency-us", in tegra_pcie_dw_parse_dt()
1129 "Failed to read ASPM L0s Entrance latency: %d\n", ret); in tegra_pcie_dw_parse_dt()
H A Dpcie-qcom-ep.c476 /* Set the L0s Exit Latency to 2us-4us = 0x6 */ in qcom_pcie_perst_deassert()
805 seq_printf(s, "L0s transition count: %u\n", in qcom_pcie_ep_link_transition_count()
H A Dpcie-dw-rockchip.c199 /* Enable L0S capability for all SoCs */ in rockchip_pcie_enable_l0s()
/linux/drivers/net/wireless/intel/iwlegacy/
H A Dcommon.c4230 /* Disable L0S exit timer (platform NMI Work/Around) */ in il_apm_init()
4235 * Disable L0s without affecting L1; in il_apm_init()
4236 * don't wait for ICH L0s (ICH bug W/A) in il_apm_init()
4246 * wake device's PCI Express link L1a -> L0s in il_apm_init()
4253 * HW bug W/A for instability in PCIe bus L0->L0S->L1 transition. in il_apm_init()
4255 * If so (likely), disable L0S, so device moves directly L0->L1; in il_apm_init()
4257 * If not (unlikely), enable L0S, so there is at least some in il_apm_init()
4263 /* L1-ASPM enabled; disable(!) L0S */ in il_apm_init()
4266 D_POWER("L1 Enabled; Disabling L0S\n"); in il_apm_init()
4268 /* L1-ASPM disabled; enable(!) L0S */ in il_apm_init()
[all …]
/linux/include/uapi/linux/
H A Dpci_regs.h494 #define PCI_EXP_DEVCAP_L0S 0x000001c0 /* L0s Acceptable Latency */
546 #define PCI_EXP_LNKCAP_ASPM_L0S 0x00000400 /* ASPM L0s Support */
548 #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
557 #define PCI_EXP_LNKCTL_ASPM_L0S 0x0001 /* L0s Enable */
/linux/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.h143 #define PM_CTRL_MAC_ASPM_CHK BIT(30) /* L0s/L1 dis by MAC based on
152 * ->L0s not L1 */
H A Datl1c_main.c1326 * Enable/disable L0s/L1 depend on link state.
1354 /* L0S/L1 enable */ in atl1c_set_aspm()
1373 /* disable l0s if link down or l2cb */ in atl1c_set_aspm()
/linux/arch/sh/drivers/pci/
H A Dpcie-sh7786.c333 /* Enable extended sync and ASPM L0s support */ in pcie_init()
/linux/arch/mips/boot/dts/brcm/
H A Dbcm7435.dtsi614 aspm-no-l0s;
H A Dbcm7425.dtsi598 aspm-no-l0s;
/linux/drivers/net/wireless/ath/ath12k/
H A Dpci.c925 ath12k_dbg(ab, ATH12K_DBG_PCI, "pci link_ctl 0x%04x L0s %d L1 %d\n", in ath12k_pci_aspm_disable()
930 /* disable L0s and L1 */ in ath12k_pci_aspm_disable()

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