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/linux/drivers/pci/controller/dwc/
H A Dpcie-spacemit-k1.c3 * SpacemiT K1 PCIe host driver
59 static void k1_pcie_toggle_soft_reset(struct k1_pcie *k1) in k1_pcie_toggle_soft_reset() argument
68 offset = k1->pmu_off + PCIE_CONTROL_LOGIC; in k1_pcie_toggle_soft_reset()
69 regmap_set_bits(k1->pmu, offset, PCIE_SOFT_RESET); in k1_pcie_toggle_soft_reset()
70 regmap_read(k1->pmu, offset, &val); in k1_pcie_toggle_soft_reset()
74 regmap_clear_bits(k1->pmu, offset, PCIE_SOFT_RESET); in k1_pcie_toggle_soft_reset()
78 static int k1_pcie_enable_resources(struct k1_pcie *k1) in k1_pcie_enable_resources() argument
80 struct dw_pcie *pci = &k1->pci; in k1_pcie_enable_resources()
101 static void k1_pcie_disable_resources(struct k1_pcie *k1) in k1_pcie_disable_resources() argument
103 struct dw_pcie *pci = &k1->pci; in k1_pcie_disable_resources()
[all …]
/linux/arch/mips/kernel/
H A Dgenex.S35 mfc0 k1, CP0_CAUSE
36 andi k1, k1, 0x7c
38 dsll k1, k1, 1
40 PTR_L k0, exception_handlers(k1)
55 mfc0 k1, CP0_CAUSE
57 andi k1, k1, 0x7c
61 beq k1, k0, handle_vced
63 beq k1, k0, handle_vcei
65 dsll k1, k1, 1
68 PTR_L k0, exception_handlers(k1)
[all …]
H A Dbmips_vec.S42 li k1, CKSEG1
43 or k0, k1
58 mfc0 k1, $22, 3
59 srl k1, 16
60 andi k1, 0x8000
61 or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
62 or k0, k1
63 li k1, 0xa0080000
64 sw k1, 0(k0)
70 li k1, CKSEG1
[all …]
H A Docteon_switch.S420 * safely modify v1,k0, k1,$10-$15, and $24. It will
436 v3mulu k1, $0, $0
439 sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
440 ori k1, $0, 1
441 v3mulu k1, k1, $0
444 sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
445 v3mulu k1, $0, $0
448 sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
505 ld k1, PT_MTP+16(sp) /* P2 */
511 mtp2 k1 /* P2 */
/linux/include/linux/
H A Dbtree-128.h22 static inline void *btree_lookup128(struct btree_head128 *head, u64 k1, u64 k2) in btree_lookup128() argument
24 u64 key[2] = {k1, k2}; in btree_lookup128()
29 u64 *k1, u64 *k2) in btree_get_prev128() argument
31 u64 key[2] = {*k1, *k2}; in btree_get_prev128()
36 *k1 = key[0]; in btree_get_prev128()
41 static inline int btree_insert128(struct btree_head128 *head, u64 k1, u64 k2, in btree_insert128() argument
44 u64 key[2] = {k1, k2}; in btree_insert128()
49 static inline int btree_update128(struct btree_head128 *head, u64 k1, u64 k2, in btree_update128() argument
52 u64 key[2] = {k1, k2}; in btree_update128()
57 static inline void *btree_remove128(struct btree_head128 *head, u64 k1, u64 k2) in btree_remove128() argument
[all …]
/linux/arch/mips/cavium-octeon/executive/
H A Dcvmx-boot-vector.c18 dmtc0 $k1, $31, 3 # Save $k1 to KScratch2
21 mfc0 $k1, $15, 1 # Ebase
25 andi $k1, 0x3ff # mask out core ID
28 sll $k1, 5
38 daddu $k0, $k0, $k1
42 dmfc0 $k1, $31, 3 # Restore $k1 from KScratch2
66 4: 40bbf803 dmtc0 k1,c0_kscratch2
69 c: 401b7801 mfc0 k1,c0_ebase
72 14: 337b03ff andi k1,k1,0x3ff
75 1c: 001bd940 sll k1,k1,0x5
[all …]
/linux/arch/sh/boards/mach-hp6xx/
H A Dpm_wakeup.S12 * k1 scratch
17 #define k1 r1 macro
21 mov #-126, k1
23 mov.b k0, @k1
25 mov.l 5f, k1
27 mov.w k0, @k1
29 mov.l 4f, k1
30 jmp @k1
/linux/arch/mips/mm/
H A Dcex-oct.S31 PTR_LA k1, cache_err_dcache
33 PTR_ADDU k1, k0, k1 /* k1 = &cache_err_dcache[core_id] */
36 sd k0, (k1)
40 mfc0 k1, CP0_STATUS
41 andi k1, k1, ST0_EXL
42 beqz k1, 1f
H A Dcex-sb1.S35 * (0x170-0x17f) are used to preserve k0, k1, and ra.
42 * save/restore k0 and k1 from low memory (Useg is direct
49 sd k1,0x178($0)
59 mfc0 k1,C0_ERRCTL
60 bgtz k1,attempt_recovery
61 sll k0,k1,1
98 li k1,1 << 26 /* ICACHE_EXTERNAL */
99 and k1,k0
100 bnez k1,unrecoverable
118 ld k1,0x178($0)
[all …]
/linux/Documentation/devicetree/bindings/spi/
H A Dspacemit,k1-spi.yaml4 $id: http://devicetree.org/schemas/spi/spacemit,k1-spi.yaml#
7 title: SpacemiT K1 SoC Serial Peripheral Interface (SPI)
13 The SpacemiT K1 SoC implements a SPI controller that has two 32-entry
15 section 18.2.1 of the K1 User Manual, found in the SpacemiT Keystone
16 K1 Documentation[1]. The controller transfers words using PIO. DMA
28 - const: spacemit,k1-spi
31 - const: spacemit,k1-spi
75 #include <dt-bindings/clock/spacemit,k1-syscon.h>
77 compatible = "spacemit,k1-spi";
H A Dfsl,spi-fsl-qspi.yaml22 - spacemit,k1-qspi
25 - const: spacemit,k1-qspi
78 const: spacemit,k1-qspi
/linux/arch/sh/kernel/cpu/sh3/
H A Dentry.S34 * ldc k1, ssr ! delay slot
68 #define k1 r1 macro
82 * k1 scratch
257 mov #0xfffffff0, k1
258 extu.b k1, k1
259 not k1, k1
260 and k1, k2 ! Mask original SR value
303 ! k1 trashed
314 stc spc, k1
316 cmp/hs k0, k1 ! test k1 (saved PC) >= k0 (saved r0)
[all …]
/linux/lib/crypto/s390/
H A Dchacha-s390.S53 #define K1 %v17 macro
90 VL K1,0,,KEY # load key
99 VREPF XB0,K1,0 # smash the key
100 VREPF XB1,K1,1
101 VREPF XB2,K1,2
102 VREPF XB3,K1,3
284 VAF XB0,XB0,K1
307 VAF XB0,XB1,K1
334 VAF XB0,XB2,K1
361 VAF XB0,XB3,K1
[all …]
/linux/drivers/phy/spacemit/
H A DKconfig6 tristate "PCIe and combo PHY driver for the SpacemiT K1 SoC"
15 PCIe-only PHYs used in the SpacemiT K1 SoC.
18 tristate "SpacemiT K1 USB 2.0 PHY support"
24 Enable this to support K1 USB 2.0 PHY driver. This driver takes care of
25 enabling and clock setup and will be used by K1 udc/ehci/otg/xhci driver.
H A DMakefile2 obj-$(CONFIG_PHY_SPACEMIT_K1_PCIE) += phy-k1-pcie.o
3 obj-$(CONFIG_PHY_SPACEMIT_K1_USB2) += phy-k1-usb2.o
/linux/lib/crypto/arm/
H A Dsha1-ce-core.S17 k1 .req q1
68 vld1.32 {k0-k1}, [ip, :128]!
94 add_update c, 0, k1, 8, 9, 10, 11
96 add_update p, 1, k1, 9, 10, 11, 8
97 add_update p, 0, k1, 10, 11, 8, 9
98 add_update p, 1, k1, 11, 8, 9, 10
99 add_update p, 0, k1, 8, 9, 10, 11
/linux/net/sunrpc/auth_gss/
H A Dgss_krb5_keys.c
/linux/arch/sh/kernel/cpu/shmobile/
H A Dsleep.S19 * k1 scratch
22 #define k1 r1 macro
249 sts pr, k1
251 and k0, k1
254 ldc k1, vbr
257 mov.l @(SH_SLEEP_SR, k1), k0
/linux/sound/soc/intel/boards/
H A Dsof_board_helpers.h66 #define SOF_LINK_ORDER(k1, k2, k3, k4, k5, k6, k7) \ argument
67 ((((k1) & SOF_LINK_ORDER_MASK) << (SOF_LINK_ORDER_SHIFT * 0)) | \
78 #define SOF_LINK_IDS(k1, k2, k3, k4, k5, k6, k7) \ argument
79 ((((k1) & SOF_LINK_IDS_MASK) << (SOF_LINK_IDS_SHIFT * 0)) | \
/linux/lib/crypto/powerpc/
H A Daes.h113 u32 k1 = swab32(in[1]); in rndkey_from_vsx() local
119 k1 = inv_mix_columns(k1); in rndkey_from_vsx()
124 out[1] = be ? k1 : k2; in rndkey_from_vsx()
125 out[2] = be ? k2 : k1; in rndkey_from_vsx()
/linux/drivers/crypto/ccp/
H A Dccp-crypto-aes-cmac.c151 /* Initialize the K1/K2 scatterlist */ in ccp_do_cmac_update()
296 /* Generate K1 and K2 */ in ccp_aes_cmac_setkey()
306 gk = (__be64 *)ctx->u.aes.k1; in ccp_aes_cmac_setkey()
313 if (ctx->u.aes.k1[0] & 0x80) { in ccp_aes_cmac_setkey()
322 ctx->u.aes.kn_len = sizeof(ctx->u.aes.k1); in ccp_aes_cmac_setkey()
323 sg_init_one(&ctx->u.aes.k1_sg, ctx->u.aes.k1, sizeof(ctx->u.aes.k1)); in ccp_aes_cmac_setkey()
/linux/lib/crypto/x86/
H A Dsha1-avx2-asm.S670 #define K1 0x5a827999 macro
677 .long K1, K1, K1, K1
678 .long K1, K1, K1, K1
/linux/arch/mips/dec/prom/
H A Dlocore.S21 la k1, mem_err
23 sw k0, 0(k1)
/linux/arch/mips/kvm/
H A Dentry.c165 /* k0/k1 not being used in host kernel context */ in kvm_mips_build_vcpu_run()
344 /* Guest k0/k1 loaded later */ in kvm_mips_build_enter_guest()
359 /* Restore the guest's k0/k1 registers */ in kvm_mips_build_enter_guest()
393 /* Save guest k1 into scratch register */ in kvm_mips_build_tlb_refill_exception()
447 /* Restore the guest's k0/k1 registers */ in kvm_mips_build_tlb_refill_exception()
479 /* Save guest k1 into scratch register */ in kvm_mips_build_exception()
526 * Both k0/k1 registers will have already been saved (k0 into the vcpu in kvm_mips_build_exit()
527 * structure, and k1 into the scratch_tmp register). in kvm_mips_build_exit()
529 * The k1 register will already contain the kvm_vcpu_arch pointer. in kvm_mips_build_exit()
534 /* Guest k0/k1 saved later */ in kvm_mips_build_exit()
[all …]
/linux/lib/crypto/riscv/
H A Dsha256-riscv64-zvknha_or_zvknhb-zvkb.S67 #define K1 v11 macro
102 .macro sha256_16rounds last, k0, k1, k2, k3
104 sha256_4rounds \last, \k1, W1, W2, W3, W0
118 vle32.v K1, (t0)
187 sha256_16rounds 0, K0, K1, K2, K3

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