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/linux/Documentation/driver-api/cxl/linux/
H A Dcxl-driver.rst40 :caption: Diagraph of CXL fabric with a host-bridge interleave memory region
191 :caption: Diagraph of CXL fabric with a host-bridge interleave memory region
242 Decoders may have one or more `Downstream Targets` if configured to interleave
248 A `Root Decoder` is logical construct of the physical address and interleave
263 of a root decoder are `Host Bridges`, which means interleave done at the root
264 decoder level is an `Inter-Host-Bridge Interleave`.
266 Only root decoders are capable of `Inter-Host-Bridge Interleave`.
274 Interleave settings in a root decoder describe how to interleave accesses among
275 the *immediate downstream targets*, not the entire interleave set.
324 is a multi-downstream-port interleave (or `Intra-Host-Bridge Interleave` for
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/linux/Documentation/driver-api/cxl/platform/example-configurations/
H A Dflexible.rst10 to configure the memory devices in various interleave or NUMA node
15 * Cross-Bridge interleave is described in one CFMWS that covers all capacity.
47 Interleave Members (2^n) : 01
48 Interleave Arithmetic : 00
62 Interleave Members (2^n) : 00
63 Interleave Arithmetic : 00
76 Interleave Members (2^n) : 00
77 Interleave Arithmetic : 00
90 Interleave Members (2^n) : 00
91 Interleave Arithmetic : 00
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H A Dhb-interleave.rst4 Cross-Host-Bridge Interleave
11 * Cross-Bridge interleave is described.
42 Interleave Members (2^n) : 01
43 Interleave Arithmetic : 00
H A Dmulti-dev-per-hb.rst12 * Intra-Bridge interleave is not described here.
34 Interleave Members (2^n) : 00
35 Interleave Arithmetic : 00
/linux/drivers/ras/amd/atl/
H A Dreg_fields.h216 * Hash Interleave Controls
299 * Interleave Address Select
311 * D18F7xE0C [DRAM Address Interleave]
314 * D18F7x20C [DRAM Address Interleave]
322 * Interleave Number of Channels
334 * D18F7xE0C [DRAM Address Interleave]
337 * D18F7x20C [DRAM Address Interleave]
347 * Interleave Number of Dies
361 * D18F7xE0C [DRAM Address Interleave]
364 * D18F7x20C [DRAM Address Interleave]
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H A Dinternal.h109 * interleave modes with a number of channels divisible by 3 or the
110 * value will be 5 for interleave modes with a number of channels
111 * divisible by 5. Power-of-two interleave modes are handled
119 * address. The other bits depend on the interleave bit position which
120 * will be bit 10 for 1K interleave stripe cases and bit 11 for 2K
121 * interleave stripe cases.
221 /* Position of the 'interleave bit'. */
362 atl_debug(ctx, "Unrecognized interleave mode: %u", ctx->map.intlv_mode); in atl_debug_on_bad_intlv_mode()
H A Ddenormalize.c38 * # of interleave bits (n): 3
39 * starting interleave bit (p): 8
58 * # of interleave bits (n): 3
59 * starting interleave bit (p): 8
66 * r = n - 1; remaining interleave bits
72 /* Make a single space at the interleave bit. */ in make_space_for_coh_st_id_split_2_1()
75 /* Done if there's only a single interleave bit. */ in make_space_for_coh_st_id_split_2_1()
79 /* Make spaces for the remaining interleave bits starting at bit 12. */ in make_space_for_coh_st_id_split_2_1()
100 pr_debug("Invalid interleave bit: %u", ctx->map.intlv_bit_pos); in make_space_for_coh_st_id_mi300()
119 * to make a gap where the interleave bits will be inserted.
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/linux/Documentation/driver-api/cxl/platform/acpi/
H A Dcedt.rst31 describes any inter-host-bridge interleave configuration that may have been
42 Interleave Members (2^n) : 01 <- Interleave configuration
43 Interleave Arithmetic : 00
60 INTRA-host-bridge interleave (multiple devices on one host bridge) is NOT
/linux/Documentation/devicetree/bindings/sound/
H A Dmax98373.txt15 interleave slot.
24 - maxim,interleave-mode : For cases where a single combined channel
29 Boolean, define to enable the interleave mode, Default : false
39 maxim,interleave-mode;
H A Dmaxim,max98925.yaml35 will be used as interleave slot.
45 maxim,interleave-mode:
50 Interleave mode provides a means to output VMON and IMON data from two
/linux/Documentation/driver-api/cxl/linux/example-configurations/
H A Dmulti-interleave.rst4 Multi-Level Interleave
11 * The CXL root is configured to interleave across the two host bridges.
144 which has the same interleave configuration as :code:`region0` (shown later).
147 which has the same interleave configuration as :code:`region0` (shown later).
326 applies the interleave across the downstream ports :code:`port1` and
359 :code:`decoder0.0`. This region describes the overall interleave configuration
360 of the interleave set. So we see there are a total of :code:`4` interleave
H A Dintra-hb-interleave.rst4 Intra-Host-Bridge Interleave
11 * The Host bridge decoder is programmed to interleave across the expanders.
143 which has the same interleave configuration memory region they belong to
234 applies the interleave across the downstream ports :code:`port1` and
260 :code:`decoder0.0`. This region describes the overall interleave configuration
261 of the interleave set.
H A Dhb-interleave.rst4 Inter-Host-Bridge Interleave
11 * The CXL root is configured to interleave across the two host bridges.
117 which has the same interleave configuration as :code:`region0` (shown later).
250 applies the interleave across the downstream ports :code:`port1` and
283 :code:`decoder0.0`. This region describes the overall interleave configuration
284 of the interleave set.
/linux/Documentation/driver-api/cxl/
H A Dtheory-of-operation.rst28 Platform firmware enumerates a menu of interleave options at the "CXL root port"
32 at which the interleave can be split. For example, platform firmware may say a
34 interleave cycles across multiple Root Ports. An intervening Switch between a
35 port and an endpoint may interleave cycles across multiple Downstream Switch
251 participate". A given expander can participate in multiple CXL.mem interleave
253 example mem3 can participate in one or more of a PMEM interleave that spans two
254 Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volatile
255 memory interleave that spans 2 Host Bridges, and a Volatile memory interleave
/linux/Documentation/admin-guide/mm/
H A Dnuma_memory_policy.rst39 up, the system default policy will be set to interleave
227 Interleave mode indexes the set of nodes specified by the
236 For allocation of page cache pages, Interleave mode indexes
258 Weighted interleave allocates pages on nodes according to a
271 Many), preferred node (Preferred) or nodemask (Bind, Interleave) is
281 mems 1-3 that sets an Interleave policy over the same set. If
282 the cpuset's mems change to 3-5, the Interleave will now occur
284 3 is allowed from the user's nodemask, the "interleave" only
302 nodes, the node (Preferred) or nodemask (Bind, Interleave) is
313 Bind or Interleave case, the third and fifth) nodes in the set of
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/linux/Documentation/ABI/testing/
H A Dsysfs-kernel-mm-mempolicy-weighted-interleave4 Description: Configuration Interface for the Weighted Interleave policy
11 The interleave weight for a memory node (N). These weights are
34 Configuration mode for weighted interleave. 'true' indicates
H A Dsysfs-bus-cxl296 configured interleave order of the decoder's dport instances.
395 decoder's position in the interleave is determined by the
397 decoders their interleave is specified by platform firmware and
408 to the next target in the interleave at address N +
420 (interleave-set) within the decode range bounded by root decoder
470 interleave set will claim. The possible interleave granularity
495 interleave configuration parameters. Once set it cannot be
532 interleave and N is the 'interleave_ways' setting for the
535 position relative to the root decoder interleave. EBUSY is
537 if the region is not in a state to accept interleave
/linux/Documentation/devicetree/bindings/net/
H A Dlantiq,pef2256.yaml89 bit/s, the data (all 32 8-bit) present in the frame are interleave with
91 correct alignment of the interleave mechanism.
93 lantiq,channel-phase = 2, the interleave schema with unused time-slots
98 interleave schema is
102 lantiq,channel-phase = 1, the interleave schema is
/linux/drivers/media/dvb-frontends/
H A Dlgs8gxx_priv.h35 #define TIM_MASK 0x20 /* Time Interleave Length Mask */
36 #define TIM_LONG 0x20 /* Time Interleave Length = 720 */
37 #define TIM_MIDDLE 0x00 /* Time Interleave Length = 240 */
/linux/drivers/mtd/chips/
H A Dcfi_util.c43 unsigned interleave = cfi_interleave(cfi); in cfi_build_cmd_addr() local
47 addr = (cmd_ofs * type) * interleave; in cfi_build_cmd_addr()
54 if (((type * interleave) > bankwidth) && ((cmd_ofs & 0xff) == 0xaa)) in cfi_build_cmd_addr()
55 addr |= (type >> 1)*interleave; in cfi_build_cmd_addr()
62 * Transforms the CFI command for the given geometry (bus width & interleave).
222 int osf = cfi->interleave * cfi->device_type; /* scale factor */ in cfi_qry_present()
302 int ofs_factor = cfi->interleave * cfi->device_type; in cfi_read_pri()
H A DKconfig128 bool "Support 1-chip flash interleave" if MTD_CFI_GEOMETRY
135 bool "Support 2-chip flash interleave" if MTD_CFI_GEOMETRY
142 bool "Support 4-chip flash interleave" if MTD_CFI_GEOMETRY
149 bool "Support 8-chip flash interleave" if MTD_CFI_GEOMETRY
/linux/sound/pci/echoaudio/
H A Dechoaudio_dsp.c788 /* Look for super-interleave (no big-endian and 8 bits) */ in set_audio_format()
789 if (format->interleave > 2) { in set_audio_format()
801 dsp_format |= format->interleave; in set_audio_format()
804 switch (format->interleave) { in set_audio_format()
814 } else if (format->interleave == 1 && in set_audio_format()
822 if (format->interleave == 2) in set_audio_format()
829 if (format->interleave == 2) in set_audio_format()
835 if (format->interleave == 2) in set_audio_format()
841 if (format->interleave == 2) in set_audio_format()
857 first channel must be set, regardless its interleave.
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/linux/drivers/nvdimm/
H A Dlabel.h74 * @nlabel: 1 per interleave-way in the region
80 * @ig: interleave granularity (1 << @ig) * 256 bytes
108 * @isetcookie: interleave set cookie
155 * @region_uuid: host interleave set identifier
/linux/tools/testing/selftests/bpf/benchs/
H A Dbench_local_storage.c187 skel->rodata->interleave = 0; in hashmap_setup()
202 skel->rodata->interleave = 0; in local_storage_cache_get_setup()
217 skel->rodata->interleave = 1; in local_storage_cache_get_interleaved_setup()
246 * cache interleaved get: like "sequential get", but interleave 4 calls to the
/linux/tools/perf/scripts/python/
H A Dintel-pt-events.py80 ap.add_argument("--interleave", type=int, nargs='?', const=4, default=0)
105 if glb_args.interleave:
127 # Output at most glb_args.interleave output strings per cpu
130 countdown = glb_args.interleave
436 if glb_args.interleave:
446 if glb_args.interleave:
467 if glb_args.interleave:

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