| /freebsd/sys/contrib/device-tree/Bindings/powerpc/nintendo/ |
| H A D | wii.txt | 11 - model : Should be "nintendo,wii"
12 - compatible : Should be "nintendo,wii"
16 This node represents the multi-function "Hollywood" chip, which packages
21 - compatible : Should be "nintendo,hollywood"
25 Represents the interface between the graphics processor and a external
30 - compatible : should be "nintendo,hollywood-vi","nintendo,flipper-vi"
31 - reg : should contain the VI registers location and length
32 - interrupt
[all...] |
| /freebsd/sys/contrib/device-tree/Bindings/mailbox/ |
| H A D | qcom-ipcc.yaml | 1 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mailbox/qcom-ipcc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. Inter-Processor Communication Controller
10 - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
13 The Inter-Processor Communication Controller (IPCC) is a centralized hardware
14 to route interrupts across various subsystems. It involves a three-level
16 entity on the Application Processor Subsystem (APSS) that wants to listen to
18 a case, the client would be Modem (client-id is 2) and the signal would be
[all …]
|
| H A D | mtk,adsp-mbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/mtk,adsp-mbox.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Allen-KH Cheng <Allen-KH.Cheng@mediatek.com>
13 The MTK ADSP mailbox Inter-Processor Communication (IPC) enables the SoC
15 The MTK ADSP mailbox IPC also provides the ability for one processor to
16 signal the other processor using interrupts.
21 - enum:
22 - mediatek,mt8186-adsp-mbox
[all …]
|
| H A D | xlnx,zynqmp-ipi-mailbox.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mailbox/xlnx,zynqmp-ip
[all...] |
| H A D | xlnx,zynqmp-ipi-mailbox.txt | 4 The Xilinx IPI(Inter Processor Interrupt) mailbox controller is to manage
8 +-------------------------------------+
10 +-------------------------------------+
11 +--------------------------------------------------+
15 +--------------------------+ |
18 +--------------------------------------------------+
19 +------------------------------------------+
20 | +----------------+ +----------------+ |
24 | +----------------+ +----------------+ |
27 +------------------------------------------+
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/timer/ |
| H A D | sifive,clint.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Palmer Dabbelt <palmer@dabbelt.com>
11 - Anup Patel <anup.patel@wdc.com>
14 SiFive (and other RISC-V) SOCs include an implementation of the SiFive
15 Core Local Interruptor (CLINT) for M-mode timer and M-mode inter-processor
16 interrupts. It directly connects to the timer and inter-processor interrupt
17 lines of various HARTs (or CPUs) so RISC-V per-HART (or per-CPU) local
19 The clock frequency of CLINT is specified via "timebase-frequency" DT
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/misc/ |
| H A D | qcom,fastrpc.txt | 3 The FastRPC implements an IPC (Inter-Processor Communication)
6 to offload tasks to the DSP and free up the application processor for
9 - compatible:
14 - label
20 - qcom,non-secure-domain:
23 Definition: Property to specify that dsp domain is non-secure.
25 - qcom,vmids:
28 Definition: Virtual machine IDs for remote processor.
30 - #address-cells
35 - #size-cells
[all …]
|
| H A D | qcom,fastrpc.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
13 The FastRPC implements an IPC (Inter-Processor Communication)
16 to offload tasks to the DSP and free up the application processor for
25 - adsp
26 - mdsp
27 - sdsp
28 - cdsp
[all …]
|
| /freebsd/sys/i386/i386/ |
| H A D | mp_machdep.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
158 for (i = *physmap_idx; i <= *physmap_idx; i -= 2) { in alloc_ap_trampoline()
165 (trunc_page(physmap[i + 1]) - round_page(physmap[i])) < in alloc_ap_trampoline()
176 if ((physmap[i + 1] - boot_address) < bootMP_size) in alloc_ap_trampoline()
177 boot_address -= round_page(bootMP_size); in alloc_ap_trampoline()
185 sizeof(*physmap) * (*physmap_idx - i + 2)); in alloc_ap_trampoline()
186 *physmap_idx -= 2; in alloc_ap_trampoline()
192 boot_address = basemem * 1024 - bootMP_size; in alloc_ap_trampoline()
210 cpu_apic_ids[i] = -1; in cpu_mp_start()
[all …]
|
| /freebsd/share/doc/psd/01.cacm/ |
| H A D | p3 | 14 An image is the current state of a pseudo-computer.
19 While the processor is executing on behalf of a process,
22 unless the appearance of an active, higher-priority
26 The user-memory part of an image is divided into three logical segments.
28 During execution, this segment is write-protected
32 virtual address space begins a non-shared, writable data segment,
81 calls that are used for file-system I/O.
89 creates an inter-process channel called a
107 inter-process communication
126 .UL arg\v'.3'\*s1\*n\v'-.3'\| ,
[all …]
|
| /freebsd/share/man/man9/ |
| H A D | mi_switch.9 | 48 function implements the machine-independent prelude to a thread context
54 Inter-Processor Interrupt (IPI).
59 .Bl -enum -offset indent
69 Involuntary preemption due to arrival of a higher-priority thread.
93 when a thread wants to voluntarily relinquish the processor.
102 .Bl -tag -offset indent -width "SWT_REMOTEWAKEIDLE"
122 Preemption by a higher-priority thread, initiated by a remote processor.
124 Idle thread preempted, initiated by a remote processor.
126 The running thread has been bound to another processor and must be switched
157 to perform the low-level context switch.
[all …]
|
| /freebsd/share/man/man4/ |
| H A D | sched_4bsd.4 | 42 .Bl -tag -width indent
44 This read-only sysctl reports the name of the active scheduler.
46 This read-write sysctl reports or sets the length of the quantum (in
47 micro-seconds) granted to a thread.
49 This read-write sysctl sets whether or not the scheduler will generate an
50 inter-processor interrupt (IPI) to an idle CPU when a thread is woken up.
54 This read-only sysctl reports whether or not the kernel is configured to
69 While a highly robust and time-tested scheduler,
71 lacks specific knowledge of how to schedule advantageously in non-symmetric
72 processor configurations, such as hyper-threading.
|
| H A D | apic.4 | 36 .Bd -ragged -offset indent
42 .Bl -ohang
56 Local APICs manage all external interrupts for a specific processor.
57 In addition, they are able to accept and generate inter-processor interrupts
63 Each local APIC includes one 32-bit programmable timer.
65 Event timer provided by the driver supports both one-shot and periodic modes.
66 Because of local APIC nature it is per-CPU.
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | marvell,mpic.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/interrupt-controller/marvell,mpic.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Marek Behún <kabel@kernel.org>
13 The top-level interrupt controller on Marvell Armada 370 and XP. On these
14 platforms it also provides inter-processor interrupts.
26 - description: main registers
27 - description: per-cpu registers
31 - description: |
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/media/ |
| H A D | mediatek,mdp3-rdma.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/media/mediatek,mdp3-rdma.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Matthias Brugger <matthias.bgg@gmail.com>
11 - Moudy Ho <moudy.ho@mediatek.com>
24 - enum:
25 - mediatek,mt8183-mdp3-rdma
26 - mediatek,mt8188-mdp3-rdma
27 - mediatek,mt8195-mdp3-rdma
[all …]
|
| /freebsd/sys/amd64/amd64/ |
| H A D | mp_machdep.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
124 cpu_apic_ids[i] = -1; in cpu_mp_start()
127 /* Install an inter-CPU IPI for cache and TLB invalidations. */ in cpu_mp_start()
131 /* Install an inter-CPU IPI for all-CPU rendezvous */ in cpu_mp_start()
135 /* Install generic inter-CPU IPI handler */ in cpu_mp_start()
139 /* Install an inter-CPU IPI for CPU stop/restart */ in cpu_mp_start()
143 /* Install an inter-CPU IPI for CPU suspend/resume */ in cpu_mp_start()
152 if (boot_cpu_id == -1) { in cpu_mp_start()
166 MPASS(kernel_pmap->pm_cr3 < (1UL << 32)); in cpu_mp_start()
[all …]
|
| /freebsd/sys/riscv/riscv/ |
| H A D | sbi_ipi.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
65 KASSERT(isrc == &sc->isrc, ("%s: not the IPI isrc", __func__)); in sbi_ipi_pic_ipi_send()
71 cpu = pc->pc_cpuid; in sbi_ipi_pic_ipi_send()
73 atomic_set_32(&sc->pending_ipis[cpu], 1u << ipi); in sbi_ipi_pic_ipi_send()
74 mask |= (1ul << pc->pc_hart); in sbi_ipi_pic_ipi_send()
90 *isrcp = &sc->isrc; in sbi_ipi_pic_ipi_setup()
112 ipi_bitmap = atomic_readandclear_32(&sc->pending_ipis[cpu]); in sbi_ipi_intr()
119 ipi = (bit - 1); in sbi_ipi_intr()
131 device_set_desc(dev, "RISC-V SBI Inter-Processor Interrupts"); in sbi_ipi_probe()
[all …]
|
| /freebsd/contrib/ntp/html/drivers/ |
| H A D | driver6.html | 1 <!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.01 Transitional//EN">
4 <meta http-equiv="content-type" content="text/html;charset=iso-8859-1">
13 <!-- #BeginDate format:En2m -->17-Jul-2014 02:17<!-- #EndDate -->
22 …Inter-Range Instrumentation Group (IRIG) standard time distribution signal. This signal is generat…
23 <p>The driver requires an audio codec or sound card with sampling rate 8 kHz and μ-law compandin…
24 …d 50 Ohms. In such cases the cable should be terminated at the line-in port with a 50-Ohm resistor…
25 …-GHz P4 running FreeBSD 6.1 is less than 20 μs with standard deviation 10 μs. Most of this i…
26 …. The Sun kernel driver has a sawtooth modulation with amplitude over 5 ms P-P and period 5.5 s. T…
30 …-modulated carrier with pulse-width modulated data bits. For IRIG-B, the carrier frequency is 1000…
31 …-Hz μ-law companded samples using separate signal filters for IRIG-B and IRIG-E, a comb filter,…
[all …]
|
| /freebsd/sys/contrib/ncsw/Peripherals/QM/ |
| H A D | qm.h | 3 � 1995-2003, 2004, 2005-2011 Freescale Semiconductor, Inc.
138 /* Corenet initiator settings. Stash request queues are 4-deep to match cores'
146 /* QM-Portal defaults */
397 * inter-processor locking only. */
400 if (fq->flags & QMAN_FQ_FLAG_LOCKED) \
401 XX_LockSpinlock(&fq->fqlock); \
405 if (fq->flags & QMAN_FQ_FLAG_LOCKED) \
406 XX_UnlockSpinlock(&fq->fqlock); \
410 * interrupts/preemption and, if FLAG_UNLOCKED isn't defined, inter-processor
412 #define NCSW_PLOCK(p) ((t_QmPortal*)(p))->irq_flags = XX_DisableAllIntr()
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/powerpc/fsl/ |
| H A D | mpic.txt | 14 - compatible
22 - reg
24 Value type: <prop-encoded-array>
29 - interrupt-controller
35 - #interrupt-cells
39 specifiers do not contain the interrupt-type or type-specific
42 - #address-cells
47 - pic-no-reset
53 configuration registers to a sane state-- masked or
60 - big-endian
[all …]
|
| /freebsd/share/doc/smm/11.timedop/ |
| H A D | timed.ms | 48 Command under contract No. N00039-84-C-0089, and by the CSELT
56 .EH 'SMM:11-%''Timed Installation and Operation'
57 .OH 'Timed Installation and Operation''SMM:11-%'
65 The algorithms implemented by the service is based on a master-slave scheme.
105 The present implementation keeps processor clocks synchronized
111 terminate (for example, because of a run-time error), or
142 augmented with point-to-point links.
143 Machines that are only connected to point-to-point,
144 non-broadcast networks may not use the time daemon.
165 This is done with the \fI\-n network\fP and \fI\-i network\fP
[all …]
|
| /freebsd/sys/net/ |
| H A D | if_types.h | 1 /*-
2 * SPDX-License-Identifier: BSD-3-Clause
41 * http://www.iana.org/assignments/smi-numbers
46 IFT_1822 = 0x2, /* old-style arpanet imp */
63 IFT_CEPT = 0x13, /* E1 - european T1 */
78 IFT_PARA = 0x22, /* parallel-port */
111 IFT_G703AT2MB = 0x43, /* Obsolete see DS1-MIB */
134 IFT_HOSTPAD = 0x5a, /* CCITT-ITU X.29 PAD Protocol */
135 IFT_TERMPAD = 0x5b, /* CCITT-ITU X.3 PAD Facility */
137 IFT_X213 = 0x5d, /* CCITT-ITU X213 */
[all …]
|
| /freebsd/sys/contrib/xen/ |
| H A D | arch-arm.h | 2 * arch-arm.h
38 * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2,
43 * is an inter-procedure-call scratch register (e.g. for use in linker
57 * EABI) and Procedure Call Standard for the ARM 64-bit Architecture
58 * (AAPCS64). Where there is a conflict the 64-bit standard should be
64 * which is mapped as Normal Inner Write-Back Outer Write-Back Inner-Shareable.
66 * - hypercall arguments passed via a pointer to guest memory.
67 * - memory shared via the grant table mechanism (including PV I/O
69 * - memory shared with the hypervisor (struct shared_info, struct
90 * All generic sub-operations
[all …]
|
| /freebsd/usr.sbin/bhyve/amd64/ |
| H A D | task_switch.c | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
93 static_assert(sizeof(struct tss32) == 104, "compile-time assertion failed");
125 if (usd->sd_gran) in usd_to_seg_desc()
129 seg_desc.access = usd->sd_type | usd->sd_dpl << 5 | usd->sd_p << 7; in usd_to_seg_desc()
130 seg_desc.access |= usd->sd_xx << 12; in usd_to_seg_desc()
131 seg_desc.access |= usd->sd_def32 << 14; in usd_to_seg_desc()
132 seg_desc.access |= usd->sd_gran << 15; in usd_to_seg_desc()
154 * Bit 2 from the selector is retained as-is in the error code. in sel_exception()
170 * and non-zero otherwise.
[all …]
|
| /freebsd/share/doc/psd/02.implement/ |
| H A D | implement | 4 .\" Copyright (C) Caldera International Inc. 2001-2002. All rights reserved.
40 .EH 'PSD:2-%''UNIX Implementation'
41 .OH 'UNIX Implementation''PSD:2-%'
55 \&\\$3\s-1\\$1\\s0\&\\$2
69 .AU "MH 2C-523" 2394
75 This paper describes in high-level terms the
120 but have that way be the least-common divisor
125 It is a soap-box platform on
159 from a read-only text segment,
165 from shared-text segments.
[all …]
|