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/freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/
H A DInstCombineInternal.h62 public InstVisitor<InstCombinerImpl, Instruction *> {
84 // Visitation implementation - Implement instruction combining for different
85 // instruction types. The semantics are as follows:
89 // otherwise - Change was made, replace I with returned instruction
91 Instruction *visitFNeg(UnaryOperator &I);
92 Instruction *visitAdd(BinaryOperator &I);
93 Instruction *visitFAdd(BinaryOperator &I);
96 Instruction *visitSub(BinaryOperator &I);
97 Instruction *visitFSub(BinaryOperator &I);
98 Instruction *visitMul(BinaryOperator &I);
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/freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/
H A Dfrontend.json5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
11 "BriefDescription": "Branch Instruction Finished",
23 "BriefDescription": "Branch Instruction completed",
71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
101 …: "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Gr…
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/
H A DLegality.cpp10 #include "llvm/SandboxIR/Instruction.h"
35 auto *I0 = cast<Instruction>(Bndl[0]); in notVectorizableBasedOnOpcodesAndTypes()
39 return cast<Instruction>(V)->getOpcode() != Opcode; in notVectorizableBasedOnOpcodesAndTypes()
55 FastMathFlags FMF0 = cast<Instruction>(Bndl[0])->getFastMathFlags(); in notVectorizableBasedOnOpcodesAndTypes()
57 return cast<Instruction>(V)->getFastMathFlags() != FMF0; in notVectorizableBasedOnOpcodesAndTypes()
70 return cast<Instruction>(V)->hasNoUnsignedWrap() != NUW0 || in notVectorizableBasedOnOpcodesAndTypes()
71 cast<Instruction>(V)->hasNoSignedWrap() != NSW0; in notVectorizableBasedOnOpcodesAndTypes()
79 case Instruction::Opcode::ZExt: in notVectorizableBasedOnOpcodesAndTypes()
80 case Instruction::Opcode::SExt: in notVectorizableBasedOnOpcodesAndTypes()
81 case Instruction::Opcode::FPToUI: in notVectorizableBasedOnOpcodesAndTypes()
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/freebsd/contrib/llvm-project/llvm/include/llvm/IR/
H A DInstruction.h1 //===-- llvm/Instruction.h - Instruction class definition -------*- C++ -*-===//
9 // This file contains the declaration of the Instruction class, which is the
42 template <> struct ilist_alloc_traits<Instruction> {
43 static inline void deleteNode(Instruction *V);
50 using InstListType = SymbolTableList<Instruction, ilist_iterator_bits<true>,
58 InsertPosition(Instruction *InsertBefore);
66 class Instruction : public User,
67 public ilist_node_with_parent<Instruction, BasicBlock,
71 using InstListType = SymbolTableList<Instruction, ilist_iterator_bits<true>,
77 /// Relative order of this instruction in its parent basic block. Used for
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H A DInstVisitor.h1 //===- InstVisitor.h - Instruction visitor templates ------------*- C++ -*-===//
21 // We operate on opaque instruction classes, so forward declare all instruction
25 #include "llvm/IR/Instruction.def"
32 /// Base class for instruction visitors
34 /// Instruction visitors are used when you want to perform different actions
61 /// The defined has 'visit' methods for Instruction, and also for BasicBlock,
64 /// Note that if you don't implement visitXXX for some instruction type,
65 /// the visitXXX method for instruction superclass will be invoked. So
69 /// The optional second template argument specifies the type that instruction
75 /// as efficient as having your own switch statement over the instruction
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H A DOperator.h21 #include "llvm/IR/Instruction.h"
42 /// Return the opcode for this Instruction or ConstantExpr.
44 if (const Instruction *I = dyn_cast<Instruction>(this)) in getOpcode()
49 /// If V is an Instruction or ConstantExpr, return its opcode.
52 if (const Instruction *I = dyn_cast<Instruction>(V)) in getOpcode()
56 return Instruction::UserOp1; in getOpcode()
59 static bool classof(const Instruction *) { return true; } in classof() argument
62 return isa<Instruction>(V) || isa<ConstantExpr>(V); in classof()
87 friend class Instruction;
127 /// Return true if the instruction is commutative
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/freebsd/contrib/llvm-project/llvm/lib/IR/
H A DInstruction.cpp1 //===-- Instruction.cpp - Implement the Instruction class -----------------===//
9 // This file implements the Instruction class for the IR library.
13 #include "llvm/IR/Instruction.h"
32 InsertPosition::InsertPosition(Instruction *InsertBefore) in InsertPosition()
38 Instruction::Instruction(Type *ty, unsigned it, AllocInfo AllocInfo, in Instruction() function in Instruction
44 assert(BB && "Instruction to insert before is not in a basic block!"); in Instruction()
49 Instruction::~Instruction() { in ~Instruction()
50 assert(!getParent() && "Instruction still linked in the program!"); in ~Instruction()
52 // Replace any extant metadata uses of this instruction with poison to in ~Instruction()
54 // - Treat Instruction like any other Value, and point its extant metadata in ~Instruction()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/
H A DGIMatchTableExecutor.h69 /// - Instruction & Operand IDs are ULEB128
94 /// Switch over the opcode on the specified instruction
95 /// - InsnID(ULEB128) - Instruction ID
102 /// Switch over the LLT on the specified instruction operand
103 /// - InsnID(ULEB128) - Instruction ID
111 /// Record the specified instruction.
113 /// - NewInsnID(ULEB128) - Instruction ID to define
114 /// - InsnID(ULEB128) - Instruction ID
123 /// Check the opcode on the specified instruction
124 /// - InsnID(ULEB128) - Instruction ID
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/freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/
H A Dother.json15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
39 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
42 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/
H A DTruncInstCombine.cpp22 // fit more values in one vectorized instruction. In addition, this optimization
34 #include "llvm/IR/Instruction.h"
46 /// Given an instruction and a container, it fills all the relevant operands of
47 /// that instruction, with respect to the Trunc expression graph optimizaton.
48 static void getRelevantOperands(Instruction *I, SmallVectorImpl<Value *> &Ops) { in getRelevantOperands()
51 case Instruction::Trunc: in getRelevantOperands()
52 case Instruction::ZExt: in getRelevantOperands()
53 case Instruction::SExt: in getRelevantOperands()
57 case Instruction::Add: in getRelevantOperands()
58 case Instruction::Sub: in getRelevantOperands()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Utils/
H A DIRNormalizer.cpp46 DenseSet<const Instruction *> NamedInstructions;
48 SmallVector<Instruction *, 16> Outputs;
54 void nameInstruction(Instruction *I);
55 void nameAsInitialInstruction(Instruction *I) const;
56 void nameAsRegularInstruction(Instruction *I);
57 void foldInstructionName(Instruction *I) const;
63 void reorderDefinition(Instruction *Definition,
64 std::stack<Instruction *> &TopologicalSort,
65 SmallPtrSet<const Instruction *, 32> &Visited) const;
66 void reorderInstructionOperandsByNames(Instruction *I) const;
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/freebsd/contrib/llvm-project/llvm/lib/SandboxIR/
H A DInstruction.cpp1 //===- Instruction.cpp - The Instructions of Sandbox IR -------------------===//
9 #include "llvm/SandboxIR/Instruction.h"
14 const char *Instruction::getOpcodeName(Opcode Opc) { in getOpcodeName()
26 llvm::Instruction *Instruction::getTopmostLLVMInstruction() const { in getTopmostLLVMInstruction()
27 Instruction *Prev = getPrevNode(); in getTopmostLLVMInstruction()
29 // If at top of the BB, return the first BB instruction. in getTopmostLLVMInstruction()
32 // Else get the Previous sandbox IR instruction's bottom IR instruction and in getTopmostLLVMInstruction()
34 llvm::Instruction *PrevBotI = cast<llvm::Instruction>(Prev->Val); in getTopmostLLVMInstruction()
38 BBIterator Instruction::getIterator() const { in getIterator()
39 auto *I = cast<llvm::Instruction>(Val); in getIterator()
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/freebsd/contrib/llvm-project/llvm/lib/FuzzMutate/
H A DOperations.cpp19 Ops.push_back(binOpDescriptor(1, Instruction::Add)); in describeFuzzerIntOps()
20 Ops.push_back(binOpDescriptor(1, Instruction::Sub)); in describeFuzzerIntOps()
21 Ops.push_back(binOpDescriptor(1, Instruction::Mul)); in describeFuzzerIntOps()
22 Ops.push_back(binOpDescriptor(1, Instruction::SDiv)); in describeFuzzerIntOps()
23 Ops.push_back(binOpDescriptor(1, Instruction::UDiv)); in describeFuzzerIntOps()
24 Ops.push_back(binOpDescriptor(1, Instruction::SRem)); in describeFuzzerIntOps()
25 Ops.push_back(binOpDescriptor(1, Instruction::URem)); in describeFuzzerIntOps()
26 Ops.push_back(binOpDescriptor(1, Instruction::Shl)); in describeFuzzerIntOps()
27 Ops.push_back(binOpDescriptor(1, Instruction::LShr)); in describeFuzzerIntOps()
28 Ops.push_back(binOpDescriptor(1, Instruction::AShr)); in describeFuzzerIntOps()
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/
H A DFloat2Int.cpp39 // If a non-mappable instruction is seen, this entire def-use graph is marked
40 // as non-transformable. If we see an instruction that converts from the
78 static Instruction::BinaryOps mapBinOpcode(unsigned Opcode) { in mapBinOpcode()
81 case Instruction::FAdd: return Instruction::Add; in mapBinOpcode()
82 case Instruction::FSub: return Instruction::Sub; in mapBinOpcode()
83 case Instruction::FMul: return Instruction::Mul; in mapBinOpcode()
92 // handle. For example, an instruction may have itself as an operand. in findRoots()
96 for (Instruction &I : BB) { in findRoots()
101 case Instruction::FPToUI: in findRoots()
102 case Instruction::FPToSI: in findRoots()
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H A DSpeculativeExecution.cpp45 // it will speculate at most one instruction. It also will not speculate if
202 // If a block has only one instruction, then that is a terminator in runOnBasicBlock()
203 // instruction so that the block does nothing. This does happen. in runOnBasicBlock()
213 static InstructionCost ComputeSpeculationCost(const Instruction *I, in ComputeSpeculationCost()
216 case Instruction::GetElementPtr: in ComputeSpeculationCost()
217 case Instruction::Add: in ComputeSpeculationCost()
218 case Instruction::Mul: in ComputeSpeculationCost()
219 case Instruction::And: in ComputeSpeculationCost()
220 case Instruction::Or: in ComputeSpeculationCost()
221 case Instruction::Select: in ComputeSpeculationCost()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Support/
H A DTargetOpcodes.def9 // This file defines the target independent instruction opcodes.
27 /// Every instruction defined here must also appear in Target.td.
37 /// KILL - This instruction is a noop that is used only to adjust the
42 /// EXTRACT_SUBREG - This instruction takes two operands: a register
48 /// INSERT_SUBREG - This instruction takes three operands: a register that
65 /// The result of this instruction is the value of the second operand inserted
68 /// first operand. This instruction just communicates information; No code
70 /// This is typically used after an instruction where the write to a subregister
74 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
76 /// used between instruction selection and MachineInstr creation, before
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/freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/SandboxVectorizer/Passes/
H A DBottomUpVec.cpp12 #include "llvm/SandboxIR/Instruction.h"
47 auto *BndlI = cast<Instruction>(BndlV); in getOperand()
53 /// \Returns the BB iterator after the lowest instruction in \p Vals, or the top
54 /// of BB if no instruction found in \p Vals.
71 assert(all_of(Bndl, [](auto *V) { return isa<Instruction>(V); }) && in createVectorInstr()
79 Bndl, cast<Instruction>(Bndl[0])->getParent()); in createVectorInstr()
81 auto Opcode = cast<Instruction>(Bndl[0])->getOpcode(); in createVectorInstr()
83 case Instruction::Opcode::ZExt: in createVectorInstr()
84 case Instruction::Opcode::SExt: in createVectorInstr()
85 case Instruction::Opcode::FPToUI: in createVectorInstr()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/
H A DInstructionPrecedenceTracking.h13 // 3. Check if the given instruction is preceeded by the first special
14 // instruction in the same block.
29 class Instruction; variable
32 // Maps a block to the topmost special instruction in it. If the value is
35 DenseMap<const BasicBlock *, const Instruction *> FirstSpecialInsts;
50 /// Returns the topmost special instruction from the block \p BB. Returns
52 LLVM_ABI const Instruction *getFirstSpecialInstruction(const BasicBlock *BB);
54 /// Returns true iff at least one instruction from the basic block \p BB is
58 /// Returns true iff the first special instruction of \p Insn's block exists
60 LLVM_ABI bool isPreceededBySpecialInstruction(const Instruction *Insn);
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/freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/
H A DSystemZTargetTransformInfo.cpp41 if (const Instruction *User = dyn_cast<Instruction>(U)) { in isUsedAsMemCpySource()
62 if (const Instruction *User = dyn_cast<Instruction>(U)) { in countNumMemAccesses()
189 Instruction *Inst) const { in getIntImmCostInst()
204 case Instruction::GetElementPtr: in getIntImmCostInst()
211 case Instruction::Store: in getIntImmCostInst()
221 case Instruction::ICmp: in getIntImmCostInst()
231 case Instruction::Add: in getIntImmCostInst()
232 case Instruction::Sub: in getIntImmCostInst()
242 case Instruction::Mul: in getIntImmCostInst()
249 case Instruction::Or: in getIntImmCostInst()
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/freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/
H A DMachineInstr.h44 class Instruction; variable
64 /// Representation of each machine instruction.
88 FrameSetup = 1 << 0, // Instruction is used as a part of
90 FrameDestroy = 1 << 1, // Instruction is used as a part of
92 BundledPred = 1 << 2, // Instruction has bundled predecessors.
93 BundledSucc = 1 << 3, // Instruction has bundled successors.
94 FmNoNans = 1 << 4, // Instruction does not support Fast
96 FmNoInfs = 1 << 5, // Instruction does not support Fast
98 FmNsz = 1 << 6, // Instruction is not required to retain
100 FmArcp = 1 << 7, // Instruction supports Fast math
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/freebsd/contrib/llvm-project/llvm/include/llvm/MC/
H A DMCInstrDesc.h1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
84 /// This holds information about one operand of a machine instruction,
110 /// operand that controls an isPredicable() instruction.
141 // Machine Instruction Flags and Description
194 /// Describe properties that are true of each instruction in the target
197 /// target instruction class, and the MachineInstr class points to this struct
236 /// that the machine instruction may include implicit register def/uses as
251 /// Return flags of this instruction.
254 /// \returns true if this instruction is emitted before instruction selection
258 /// Return true if this instruction can have a variable number of
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/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/
H A DInstructionWorklist.h16 #include "llvm/IR/Instruction.h"
26 SmallVector<Instruction *, 256> Worklist;
27 DenseMap<Instruction *, unsigned> WorklistMap;
31 SmallSetVector<Instruction *, 16> Deferred;
41 /// Add instruction to the worklist.
44 void add(Instruction *I) { in add()
49 /// Add value to the worklist if it is an instruction.
52 if (Instruction *I = dyn_cast<Instruction>(V)) in addValue()
56 /// Push the instruction onto the worklist stack.
58 void push(Instruction *I) { in push()
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/freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/InstCombine/
H A DInstCombiner.h44 /// The core instruction combiner logic.
244 bool canFreelyInvertAllUsersOf(Instruction *V, Value *IgnoredUser) { in canFreelyInvertAllUsersOf()
250 auto *I = cast<Instruction>(U.getUser()); in canFreelyInvertAllUsersOf()
252 case Instruction::Select: in canFreelyInvertAllUsersOf()
258 case Instruction::Br: in canFreelyInvertAllUsersOf()
261 case Instruction::Xor: // Can invert 'xor' if it's a 'not', by ignoring in canFreelyInvertAllUsersOf()
291 case Instruction::SRem: // X % 1 = 0 in getSafeVectorConstantForBinop()
292 case Instruction::URem: // X %u 1 = 0 in getSafeVectorConstantForBinop()
295 case Instruction::FRem: // X % 1.0 (doesn't simplify, but it is safe) in getSafeVectorConstantForBinop()
304 case Instruction::Shl: // 0 << X = 0 in getSafeVectorConstantForBinop()
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/freebsd/contrib/llvm-project/llvm/lib/Target/ARM/
H A DMVELaneInterleavingPass.cpp10 // a single sext/zext or trunc instruction that takes the bottom half of a
16 // instruction, we often have to turn sext/zext/trunc into a series of lane
58 #include "llvm/IR/Instruction.h"
109 static bool isProfitableToInterleave(SmallSetVector<Instruction *, 4> &Exts, in isProfitableToInterleave() argument
110 SmallSetVector<Instruction *, 4> &Truncs) { in isProfitableToInterleave()
140 cast<Instruction>(*E->user_begin())->getOpcode() != Instruction::Mul) { in isProfitableToInterleave()
148 static bool tryInterleave(Instruction *Start, in tryInterleave()
149 SmallPtrSetImpl<Instruction *> &Visited) { in tryInterleave()
152 if (!isa<Instruction>(Start->getOperand(0))) in tryInterleave()
156 std::vector<Instruction *> Worklist; in tryInterleave()
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/freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/
H A Dtranslation.json20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t…
65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
80 …": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on …
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
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