| /freebsd/contrib/llvm-project/llvm/lib/Transforms/InstCombine/ |
| H A D | InstCombineInternal.h | 64 public InstVisitor<InstCombinerImpl, Instruction *> {
86 // Visitation implementation - Implement instruction combining for different
87 // instruction types. The semantics are as follows:
91 // otherwise - Change was made, replace I with returned instruction
93 Instruction *visitFNeg(UnaryOperator &I);
94 Instruction *visitAdd(BinaryOperator &I);
95 Instruction *visitFAdd(BinaryOperator &I);
98 Instruction *visitSub(BinaryOperator &I);
99 Instruction *visitFSub(BinaryOperator &I);
100 Instruction *visitMul(BinaryOperator &I);
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| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power8/ |
| H A D | frontend.json | 5 …"BriefDescription": "Branch instruction completed with a target address less than current instruct…
11 "BriefDescription": "Branch Instruction Finished",
23 "BriefDescription": "Branch Instruction completed",
71 …ption": "Initial and Final Pump Scope was chip pump (prediction=correct) for an instruction fetch",
72 …ope and data sourced across this scope was chip pump (prediction=correct) for an instruction fetch"
89 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
90 …Instruction cache was reloaded with Modified (M) data from another chip's L2 or L3 on a different …
95 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
96 …Instruction cache was reloaded with Shared (S) data from another chip's L2 or L3 on a different No…
101 …: "The processor's Instruction cache was reloaded from another chip's L4 on a different Node or Gr…
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|
| /freebsd/contrib/llvm-project/llvm/lib/IR/ |
| H A D | Instruction.cpp | 1 //===-- Instruction.cpp - Implement the Instruction class -----------------===//
9 // This file implements the Instruction class for the IR library.
13 #include "llvm/IR/Instruction.h"
29 InsertPosition::InsertPosition(Instruction *InsertBefore) in InsertPosition()
35 Instruction::Instruction(Type *ty, unsigned it, Use *Ops, unsigned NumOps, in Instruction() function in Instruction
41 assert(BB && "Instruction to insert before is not in a basic block!"); in Instruction()
46 Instruction::~Instruction() { in ~Instruction()
47 assert(!getParent() && "Instruction still linked in the program!"); in ~Instruction()
49 // Replace any extant metadata uses of this instruction with undef to in ~Instruction()
51 // - Treat Instruction like any other Value, and point its extant metadata in ~Instruction()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/IR/ |
| H A D | Instruction.h | 1 //===-- llvm/Instruction.h - Instruction class definition -------*- C++ -*-===//
9 // This file contains the declaration of the Instruction class, which is the
41 template <> struct ilist_alloc_traits<Instruction> {
42 static inline void deleteNode(Instruction *V);
49 using InstListType = SymbolTableList<Instruction, ilist_iterator_bits<true>,
57 InsertPosition(Instruction *InsertBefore);
65 class Instruction : public User,
66 public ilist_node_with_parent<Instruction, BasicBlock,
70 using InstListType = SymbolTableList<Instruction, ilist_iterator_bits<true>,
76 /// Relative order of this instruction in its parent basic block. Used for
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|
| H A D | InstVisitor.h | 1 //===- InstVisitor.h - Instruction visitor templates ------------*- C++ -*-===//
21 // We operate on opaque instruction classes, so forward declare all instruction
25 #include "llvm/IR/Instruction.def"
32 /// Base class for instruction visitors
34 /// Instruction visitors are used when you want to perform different actions
61 /// The defined has 'visit' methods for Instruction, and also for BasicBlock,
64 /// Note that if you don't implement visitXXX for some instruction type,
65 /// the visitXXX method for instruction superclass will be invoked. So
69 /// The optional second template argument specifies the type that instruction
75 /// as efficient as having your own switch statement over the instruction
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| H A D | Instructions.h | 1 //===- llvm/Instructions.h - Instruction subclass definitions ---*- C++ -*-===//
10 // Instruction class. This is meant to be an easy way to get access to all
11 // instruction subclasses.
31 #include "llvm/IR/Instruction.h"
60 /// an instruction to allocate memory on the stack
72 // Note: Instruction needs to be a friend here to call cloneImpl.
73 friend class Instruction;
88 /// instruction that is not 1.
98 return cast<PointerType>(Instruction::getType()); in getType()
114 /// Return the type that is being allocated by the instruction.
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|
| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Vectorize/ |
| H A D | VPlanAnalysis.cpp | 13 #include "llvm/IR/Instruction.h"
46 if (Instruction::isBinaryOp(Opcode) || Instruction::isUnaryOp(Opcode)) in inferScalarTypeForRecipe()
50 case Instruction::Select: { in inferScalarTypeForRecipe()
58 case Instruction::ICmp: in inferScalarTypeForRecipe()
92 case Instruction::ICmp: in inferScalarTypeForRecipe()
93 case Instruction::FCmp: in inferScalarTypeForRecipe()
95 case Instruction::UDiv: in inferScalarTypeForRecipe()
96 case Instruction::SDiv: in inferScalarTypeForRecipe()
97 case Instruction::SRem: in inferScalarTypeForRecipe()
98 case Instruction::URem: in inferScalarTypeForRecipe()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/GlobalISel/ |
| H A D | GIMatchTableExecutor.h | 65 /// - Instruction & Operand IDs are ULEB128
90 /// Switch over the opcode on the specified instruction
91 /// - InsnID(ULEB128) - Instruction ID
98 /// Switch over the LLT on the specified instruction operand
99 /// - InsnID(ULEB128) - Instruction ID
107 /// Record the specified instruction.
109 /// - NewInsnID(ULEB128) - Instruction ID to define
110 /// - InsnID(ULEB128) - Instruction ID
119 /// Check the opcode on the specified instruction
120 /// - InsnID(ULEB128) - Instruction ID
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| /freebsd/contrib/llvm-project/llvm/lib/Target/LoongArch/MCTargetDesc/ |
| H A D | LoongArchFixupKinds.h | 32 // 20-bit fixup corresponding to %abs_hi20(foo) for instruction lu12i.w.
34 // 12-bit fixup corresponding to %abs_lo12(foo) for instruction ori.
36 // 20-bit fixup corresponding to %abs64_lo20(foo) for instruction lu32i.d.
38 // 12-bit fixup corresponding to %abs_hi12(foo) for instruction lu52i.d.
40 // 20-bit fixup corresponding to %le_hi20(foo) for instruction lu12i.w.
42 // 12-bit fixup corresponding to %le_lo12(foo) for instruction ori.
44 // 20-bit fixup corresponding to %le64_lo20(foo) for instruction lu32i.d.
46 // 12-bit fixup corresponding to %le64_hi12(foo) for instruction lu52i.d.
57 // 20-bit fixup corresponding to %pc_hi20(foo) for instruction pcalau12i.
62 // 20-bit fixup corresponding to %pc64_lo20(foo) for instruction lu32i.d.
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/fujitsu/a64fx/ |
| H A D | other.json | 15 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
18 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
21 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
24 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
27 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
30 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
33 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
36 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
39 …"PublicDescription": "This event counts every cycle that no instruction was committed because the …
42 …"BriefDescription": "This event counts every cycle that no instruction was committed because the o…
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/AggressiveInstCombine/ |
| H A D | TruncInstCombine.cpp | 22 // fit more values in one vectorized instruction. In addition, this optimization
34 #include "llvm/IR/Instruction.h"
46 /// Given an instruction and a container, it fills all the relevant operands of
47 /// that instruction, with respect to the Trunc expression graph optimizaton.
48 static void getRelevantOperands(Instruction *I, SmallVectorImpl<Value *> &Ops) { in getRelevantOperands()
51 case Instruction::Trunc: in getRelevantOperands()
52 case Instruction::ZExt: in getRelevantOperands()
53 case Instruction::SExt: in getRelevantOperands()
57 case Instruction::Add: in getRelevantOperands()
58 case Instruction in getRelevantOperands()
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| /freebsd/contrib/llvm-project/llvm/lib/FuzzMutate/ |
| H A D | Operations.cpp | 19 Ops.push_back(binOpDescriptor(1, Instruction::Add)); in describeFuzzerIntOps()
20 Ops.push_back(binOpDescriptor(1, Instruction::Sub)); in describeFuzzerIntOps()
21 Ops.push_back(binOpDescriptor(1, Instruction::Mul)); in describeFuzzerIntOps()
22 Ops.push_back(binOpDescriptor(1, Instruction::SDiv)); in describeFuzzerIntOps()
23 Ops.push_back(binOpDescriptor(1, Instruction::UDiv)); in describeFuzzerIntOps()
24 Ops.push_back(binOpDescriptor(1, Instruction::SRem)); in describeFuzzerIntOps()
25 Ops.push_back(binOpDescriptor(1, Instruction::URem)); in describeFuzzerIntOps()
26 Ops.push_back(binOpDescriptor(1, Instruction::Shl)); in describeFuzzerIntOps()
27 Ops.push_back(binOpDescriptor(1, Instruction::LShr)); in describeFuzzerIntOps()
28 Ops.push_back(binOpDescriptor(1, Instruction::AShr)); in describeFuzzerIntOps()
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| /freebsd/contrib/llvm-project/llvm/lib/Transforms/Scalar/ |
| H A D | Float2Int.cpp | 39 // If a non-mappable instruction is seen, this entire def-use graph is marked
40 // as non-transformable. If we see an instruction that converts from the
78 static Instruction::BinaryOps mapBinOpcode(unsigned Opcode) { in mapBinOpcode()
81 case Instruction::FAdd: return Instruction::Add; in mapBinOpcode()
82 case Instruction::FSub: return Instruction::Sub; in mapBinOpcode()
83 case Instruction::FMul: return Instruction::Mul; in mapBinOpcode()
92 // handle. For example, an instruction may have itself as an operand. in findRoots()
96 for (Instruction &I : BB) { in findRoots()
101 case Instruction::FPToUI: in findRoots()
102 case Instruction::FPToSI: in findRoots()
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|
| H A D | SpeculativeExecution.cpp | 45 // it will speculate at most one instruction. It also will not speculate if
202 // If a block has only one instruction, then that is a terminator in runOnBasicBlock()
203 // instruction so that the block does nothing. This does happen. in runOnBasicBlock()
213 static InstructionCost ComputeSpeculationCost(const Instruction *I, in ComputeSpeculationCost()
216 case Instruction::GetElementPtr: in ComputeSpeculationCost()
217 case Instruction::Add: in ComputeSpeculationCost()
218 case Instruction::Mul: in ComputeSpeculationCost()
219 case Instruction::And: in ComputeSpeculationCost()
220 case Instruction::Or: in ComputeSpeculationCost()
221 case Instruction::Select: in ComputeSpeculationCost()
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| /freebsd/contrib/llvm-project/llvm/lib/Target/SystemZ/ |
| H A D | SystemZTargetTransformInfo.cpp | 40 if (const Instruction *User = dyn_cast<Instruction>(U)) { in isUsedAsMemCpySource()
110 Instruction *Inst) { in getIntImmCostInst()
125 case Instruction::GetElementPtr: in getIntImmCostInst()
132 case Instruction::Store: in getIntImmCostInst()
142 case Instruction::ICmp: in getIntImmCostInst()
152 case Instruction::Add: in getIntImmCostInst()
153 case Instruction::Sub: in getIntImmCostInst()
163 case Instruction::Mul: in getIntImmCostInst()
170 case Instruction::Or: in getIntImmCostInst()
171 case Instruction::Xor: in getIntImmCostInst()
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|
| /freebsd/contrib/llvm-project/llvm/include/llvm/Analysis/ |
| H A D | InstructionPrecedenceTracking.h | 13 // 3. Check if the given instruction is preceeded by the first special
14 // instruction in the same block.
28 class Instruction; variable
31 // Maps a block to the topmost special instruction in it. If the value is
34 DenseMap<const BasicBlock *, const Instruction *> FirstSpecialInsts;
52 /// Returns the topmost special instruction from the block \p BB. Returns
54 const Instruction *getFirstSpecialInstruction(const BasicBlock *BB);
56 /// Returns true iff at least one instruction from the basic block \p BB is
60 /// Returns true iff the first special instruction of \p Insn's block exists
62 bool isPreceededBySpecialInstruction(const Instruction *Insn);
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|
| H A D | MustExecute.h | 1 //===- MustExecute.h - Is an instruction known to execute--------*- C++ -*-===//
9 /// Contains a collection of routines for determining if a given instruction is
11 /// common example is an instruction within a loop being provably executed if we
14 /// There are two interfaces available to determine if an instruction is
40 class Instruction; variable
80 /// instruction that may throw or otherwise exit abnormally.
95 /// Returns true if the instruction in a loop is guaranteed to execute at
97 virtual bool isGuaranteedToExecute(const Instruction &Inst,
111 bool MayThrow = false; // The current loop contains an instruction which
122 bool isGuaranteedToExecute(const Instruction
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| H A D | IVDescriptors.h | 26 class Instruction;
75 RecurrenceDescriptor(Value *Start, Instruction *Exit, StoreInst *Store, in RecurrenceDescriptor()
76 RecurKind K, FastMathFlags FMF, Instruction *ExactFP, in RecurrenceDescriptor()
78 SmallPtrSetImpl<Instruction *> &CI, in RecurrenceDescriptor()
90 InstDesc(bool IsRecur, Instruction *I, Instruction *ExactFP = nullptr)
94 InstDesc(Instruction *I, RecurKind K, Instruction *ExactFP = nullptr)
102 Instruction *getExactFPMathInst() const { return ExactFPMathInst; } in getExactFPMathInst()
106 Instruction *getPatternIns
27 class Instruction; global() variable
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Support/ |
| H A D | TargetOpcodes.def | 9 // This file defines the target independent instruction opcodes.
27 /// Every instruction defined here must also appear in Target.td.
37 /// KILL - This instruction is a noop that is used only to adjust the
42 /// EXTRACT_SUBREG - This instruction takes two operands: a register
48 /// INSERT_SUBREG - This instruction takes three operands: a register that
60 /// The result of this instruction is the value of the second operand inserted
63 /// first operand. This instruction just communicates information; No code
65 /// This is typically used after an instruction where the write to a subregister
69 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
71 /// used between instruction selection and MachineInstr creation, before
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| /freebsd/contrib/llvm-project/llvm/include/llvm/CodeGen/ |
| H A D | MachineInstr.h | 42 class Instruction; variable
61 /// Representation of each machine instruction.
85 FrameSetup = 1 << 0, // Instruction is used as a part of
87 FrameDestroy = 1 << 1, // Instruction is used as a part of
89 BundledPred = 1 << 2, // Instruction has bundled predecessors.
90 BundledSucc = 1 << 3, // Instruction has bundled successors.
91 FmNoNans = 1 << 4, // Instruction does not support Fast
93 FmNoInfs = 1 << 5, // Instruction does not support Fast
95 FmNsz = 1 << 6, // Instruction is not required to retain
97 FmArcp = 1 << 7, // Instruction supports Fast math
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/InstCombine/ |
| H A D | InstCombiner.h | 43 /// The core instruction combiner logic.
140 if (isa<Instruction>(V)) { in getComplexity()
248 bool canFreelyInvertAllUsersOf(Instruction *V, Value *IgnoredUser) { in canFreelyInvertAllUsersOf()
254 auto *I = cast<Instruction>(U.getUser()); in canFreelyInvertAllUsersOf()
256 case Instruction::Select: in canFreelyInvertAllUsersOf()
262 case Instruction::Br: in canFreelyInvertAllUsersOf()
265 case Instruction::Xor: // Can invert 'xor' if it's a 'not', by ignoring in canFreelyInvertAllUsersOf()
295 case Instruction::SRem: // X % 1 = 0 in getSafeVectorConstantForBinop()
296 case Instruction::URem: // X %u 1 = 0 in getSafeVectorConstantForBinop()
299 case Instruction::FRem: // X % 1.0 (doesn't simplify, but it is safe) in getSafeVectorConstantForBinop()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/Transforms/Utils/ |
| H A D | InstructionWorklist.h | 16 #include "llvm/IR/Instruction.h"
26 SmallVector<Instruction *, 256> Worklist;
27 DenseMap<Instruction *, unsigned> WorklistMap;
31 SmallSetVector<Instruction *, 16> Deferred;
41 /// Add instruction to the worklist.
44 void add(Instruction *I) { in add()
49 /// Add value to the worklist if it is an instruction.
52 if (Instruction *I = dyn_cast<Instruction>(V)) in addValue()
56 /// Push the instruction onto the worklist stack.
58 void push(Instruction *I) { in push()
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| /freebsd/contrib/llvm-project/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 1 //===-- llvm/MC/MCInstrDesc.h - Instruction Descriptors -*- C++ -*-===//
83 /// This holds information about one operand of a machine instruction,
109 /// operand that controls an isPredicable() instruction.
140 // Machine Instruction Flags and Description
193 /// Describe properties that are true of each instruction in the target
196 /// target instruction class, and the MachineInstr class points to this struct
235 /// that the machine instruction may include implicit register def/uses as
250 /// Return flags of this instruction.
253 /// \returns true if this instruction is emitted before instruction selectio
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| /freebsd/lib/libpmc/pmu-events/arch/powerpc/power9/ |
| H A D | translation.json | 20 "BriefDescription": "Double-Precion or Quad-Precision instruction completed"
35 …chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction side request"
45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin…
50 "BriefDescription": "LSU Finished a PPC instruction (up to 4 per cycle)"
55 …: "Cycles during which the marked instruction is next to complete (completion is held up because t…
65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi…
75 …ared or modified data from another core's L2/L3 on the same chip due to a instruction side request"
80 …": "The processor's Instruction cache was reloaded with Shared (S) data from another core's L2 on …
100 …e TLB from another chip's L4 on the same Node or Group ( Remote) due to a instruction side request"
115 …"BriefDescription": "Finish stall because the NTF instruction was a vector instruction issued to t…
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| /freebsd/contrib/llvm-project/llvm/lib/Target/ARM/ |
| H A D | MVELaneInterleavingPass.cpp | 10 // a single sext/zext or trunc instruction that takes the bottom half of a
16 // instruction, we often have to turn sext/zext/trunc into a series of lane
61 #include "llvm/IR/Instruction.h"
115 static bool isProfitableToInterleave(SmallSetVector<Instruction *, 4> &Exts, in isProfitableToInterleave() argument
116 SmallSetVector<Instruction *, 4> &Truncs) { in isProfitableToInterleave()
146 cast<Instruction>(*E->user_begin())->getOpcode() != Instruction::Mul) { in isProfitableToInterleave()
154 static bool tryInterleave(Instruction *Start, in tryInterleave()
155 SmallPtrSetImpl<Instruction *> &Visited) { in tryInterleave()
158 if (!isa<Instruction>(Start->getOperand(0))) in tryInterleave()
162 std::vector<Instruction *> Worklist; in tryInterleave()
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|