xref: /linux/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v5.yaml (revision 63eb28bb1402891b1ad2be02a530f29a9dd7f1cd) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/interrupt-controller/arm,gic-v5.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: ARM Generic Interrupt Controller, version 5
8
9maintainers:
10  - Lorenzo Pieralisi <lpieralisi@kernel.org>
11  - Marc Zyngier <maz@kernel.org>
12
13description: |
14  The GICv5 architecture defines the guidelines to implement GICv5
15  compliant interrupt controllers for AArch64 systems.
16
17  The GICv5 specification can be found at
18  https://developer.arm.com/documentation/aes0070
19
20  The GICv5 architecture is composed of multiple components:
21    - one or more IRS (Interrupt Routing Service)
22    - zero or more ITS (Interrupt Translation Service)
23
24  The architecture defines:
25    - PE-Private Peripheral Interrupts (PPI)
26    - Shared Peripheral Interrupts (SPI)
27    - Logical Peripheral Interrupts (LPI)
28
29allOf:
30  - $ref: /schemas/interrupt-controller.yaml#
31
32properties:
33  compatible:
34    const: arm,gic-v5
35
36  "#address-cells":
37    enum: [ 1, 2 ]
38
39  "#size-cells":
40    enum: [ 1, 2 ]
41
42  ranges: true
43
44  "#interrupt-cells":
45    description: |
46      The 1st cell corresponds to the INTID.Type field in the INTID; 1 for PPI,
47      3 for SPI. LPI interrupts must not be described in the bindings since
48      they are allocated dynamically by the software component managing them.
49
50      The 2nd cell contains the interrupt INTID.ID field.
51
52      The 3rd cell is the flags, encoded as follows:
53      bits[3:0] trigger type and level flags.
54
55        1 = low-to-high edge triggered
56        2 = high-to-low edge triggered
57        4 = active high level-sensitive
58        8 = active low level-sensitive
59
60    const: 3
61
62  interrupt-controller: true
63
64  interrupts:
65    description:
66      The VGIC maintenance interrupt.
67    maxItems: 1
68
69required:
70  - compatible
71  - "#address-cells"
72  - "#size-cells"
73  - ranges
74  - "#interrupt-cells"
75  - interrupt-controller
76
77patternProperties:
78  "^irs@[0-9a-f]+$":
79    type: object
80    description:
81      GICv5 has one or more Interrupt Routing Services (IRS) that are
82      responsible for handling IRQ state and routing.
83
84    additionalProperties: false
85
86    properties:
87      compatible:
88        const: arm,gic-v5-irs
89
90      reg:
91        minItems: 1
92        items:
93          - description: IRS config frames
94          - description: IRS setlpi frames
95
96      reg-names:
97        description:
98          Describe config and setlpi frames that are present.
99          "ns-" stands for non-secure, "s-" for secure, "realm-" for realm
100          and "el3-" for EL3.
101        minItems: 1
102        maxItems: 8
103        items:
104          enum: [ ns-config, s-config, realm-config, el3-config, ns-setlpi,
105                  s-setlpi, realm-setlpi, el3-setlpi ]
106
107      "#address-cells":
108        enum: [ 1, 2 ]
109
110      "#size-cells":
111        enum: [ 1, 2 ]
112
113      ranges: true
114
115      dma-noncoherent:
116        description:
117          Present if the GIC IRS permits programming shareability and
118          cacheability attributes but is connected to a non-coherent
119          downstream interconnect.
120
121      cpus:
122        description:
123          CPUs managed by the IRS.
124
125      arm,iaffids:
126        $ref: /schemas/types.yaml#/definitions/uint16-array
127        description:
128          Interrupt AFFinity ID (IAFFID) associated with the CPU whose
129          CPU node phandle is at the same index in the cpus array.
130
131    patternProperties:
132      "^its@[0-9a-f]+$":
133        type: object
134        description:
135          GICv5 has zero or more Interrupt Translation Services (ITS) that are
136          used to route Message Signalled Interrupts (MSI) to the CPUs. Each
137          ITS is connected to an IRS.
138        additionalProperties: false
139
140        properties:
141          compatible:
142            const: arm,gic-v5-its
143
144          reg:
145            items:
146              - description: ITS config frames
147
148          reg-names:
149            description:
150              Describe config frames that are present.
151              "ns-" stands for non-secure, "s-" for secure, "realm-" for realm
152              and "el3-" for EL3.
153            minItems: 1
154            maxItems: 4
155            items:
156              enum: [ ns-config, s-config, realm-config, el3-config ]
157
158          "#address-cells":
159            enum: [ 1, 2 ]
160
161          "#size-cells":
162            enum: [ 1, 2 ]
163
164          ranges: true
165
166          dma-noncoherent:
167            description:
168              Present if the GIC ITS permits programming shareability and
169              cacheability attributes but is connected to a non-coherent
170              downstream interconnect.
171
172        patternProperties:
173          "^msi-controller@[0-9a-f]+$":
174            type: object
175            description:
176              GICv5 ITS has one or more translate register frames.
177            additionalProperties: false
178
179            properties:
180              reg:
181                items:
182                  - description: ITS translate frames
183
184              reg-names:
185                description:
186                  Describe translate frames that are present.
187                  "ns-" stands for non-secure, "s-" for secure, "realm-" for realm
188                  and "el3-" for EL3.
189                minItems: 1
190                maxItems: 4
191                items:
192                  enum: [ ns-translate, s-translate, realm-translate, el3-translate ]
193
194              "#msi-cells":
195                description:
196                  The single msi-cell is the DeviceID of the device which will
197                  generate the MSI.
198                const: 1
199
200              msi-controller: true
201
202            required:
203              - reg
204              - reg-names
205              - "#msi-cells"
206              - msi-controller
207
208        required:
209          - compatible
210          - reg
211          - reg-names
212
213    required:
214      - compatible
215      - reg
216      - reg-names
217      - cpus
218      - arm,iaffids
219
220additionalProperties: false
221
222examples:
223  - |
224    interrupt-controller {
225      compatible = "arm,gic-v5";
226
227      #interrupt-cells = <3>;
228      interrupt-controller;
229
230      #address-cells = <1>;
231      #size-cells = <1>;
232      ranges;
233
234      interrupts = <1 25 4>;
235
236      irs@2f1a0000 {
237        compatible = "arm,gic-v5-irs";
238        reg = <0x2f1a0000 0x10000>;  // IRS_CONFIG_FRAME
239        reg-names = "ns-config";
240
241        #address-cells = <1>;
242        #size-cells = <1>;
243        ranges;
244
245        cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>, <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
246        arm,iaffids = /bits/ 16 <0 1 2 3 4 5 6 7>;
247
248        its@2f120000 {
249          compatible = "arm,gic-v5-its";
250          reg = <0x2f120000 0x10000>;   // ITS_CONFIG_FRAME
251          reg-names = "ns-config";
252
253          #address-cells = <1>;
254          #size-cells = <1>;
255          ranges;
256
257          msi-controller@2f130000 {
258            reg = <0x2f130000 0x10000>;   // ITS_TRANSLATE_FRAME
259            reg-names = "ns-translate";
260
261            #msi-cells = <1>;
262            msi-controller;
263          };
264        };
265      };
266    };
267...
268