| /linux/arch/sparc/kernel/ |
| H A D | iommu.c | 2 /* iommu.c: Generic sparc64 IOMMU support.
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
49 /* Must be invoked under the IOMMU lock. */
52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
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| H A D | iommu-common.c | 3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
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| H A D | pci_sun4v.c | 21 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
58 unsigned long prot; /* IOMMU page protections */
78 static inline bool iommu_use_atu(struct iommu *iommu, u64 mask) in iommu_use_atu() argument
80 return iommu->atu && mask > DMA_BIT_MASK(32); in iommu_use_atu()
102 if (!iommu_use_atu(pbm->iommu, mask)) { in iommu_batch_flush()
109 pr_err_ratelimited("%s: IOMMU map of [%08lx:%08llx:%lx:%lx:%lx] failed with status %ld\n", in iommu_batch_flush()
119 iotsb_num = pbm->iommu->atu->iotsb->iotsb_num; in iommu_batch_flush()
188 struct iommu *iommu; in dma_4v_alloc_coherent() local
213 iommu = dev->archdata.iommu; in dma_4v_alloc_coherent()
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| H A D | sbus.c | 37 #define IOMMU_CONTROL (0x2400UL - 0x2400UL) /* IOMMU control register */
39 #define IOMMU_FLUSH (0x2410UL - 0x2400UL) /* IOMMU flush register */
42 #define IOMMU_LRUDIAG (0x4500UL - 0x2400UL) /* IOMMU LRU queue diagnostics */
63 struct iommu *iommu = dev->archdata.iommu; in sbus_set_sbus64() local
78 cfg_reg = iommu->write_complete_reg; in sbus_set_sbus64()
213 struct iommu *iommu = op->dev.archdata.iommu; in sbus_build_irq() local
214 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sbus_build_irq()
275 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ue_handler() local
276 unsigned long reg_base = iommu->write_complete_reg - 0x2000UL; in sysio_ue_handler()
349 struct iommu *iommu = op->dev.archdata.iommu; in sysio_ce_handler() local
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| /linux/drivers/iommu/ |
| H A D | sun50i-iommu.c | 14 #include <linux/iommu.h>
29 #include "iommu-pages.h"
101 struct iommu_device iommu; member
103 /* Lock to modify the IOMMU registers */
125 struct sun50i_iommu *iommu; member
138 static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) in iommu_read() argument
140 return readl(iommu->base + offset); in iommu_read()
143 static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value) in iommu_write() argument
145 writel(value, iommu->base + offset); in iommu_write()
149 * The Allwinner H6 IOMMU uses a 2-level page table.
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| H A D | iommu-sysfs.c | 3 * IOMMU sysfs class support
10 #include <linux/iommu.h>
16 * As devices are added to the IOMMU, we'll add links to the group.
38 .name = "iommu",
50 * Init the struct device for the IOMMU. IOMMU specific attributes can
52 * IOMMU type.
54 int iommu_device_sysfs_add(struct iommu_device *iommu, in iommu_device_sysfs_add() argument
62 iommu->dev = kzalloc_obj(*iommu->dev); in iommu_device_sysfs_add()
63 if (!iommu->dev) in iommu_device_sysfs_add()
66 device_initialize(iommu->dev); in iommu_device_sysfs_add()
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| H A D | omap-iommu.c | 3 * omap iommu: tlb and pagetable primitives
18 #include <linux/iommu.h>
19 #include <linux/omap-iommu.h>
30 #include <linux/platform_data/iommu-omap.h>
33 #include "omap-iommu.h"
57 * @dom: generic iommu domain handle
325 * load_iotlb_entry - Set an iommu tlb entry
326 * @obj: target iommu
327 * @e: an iommu tlb entry info
401 * flush_iotlb_page - Clear an iommu tlb entry
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| /linux/drivers/iommu/amd/ |
| H A D | init.c | 19 #include <linux/amd-iommu.h>
25 #include <asm/iommu.h>
38 #include "../iommu-pages.h"
98 * structure describing one IOMMU in the ACPI table. Typically followed by one
118 * A device entry describing which devices a specific IOMMU translates and
139 * An AMD IOMMU memory definition structure. It defines things like exclusion
238 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
240 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
243 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
245 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
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| H A D | iommu.c | 23 #include <linux/iommu-helper.h>
25 #include <linux/amd-iommu.h>
39 #include <asm/iommu.h>
43 #include <linux/generic_pt/iommu.h>
48 #include "../iommu-pages.h"
67 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
75 static void set_dte_entry(struct amd_iommu *iommu,
84 static void iommu_flush_dte_sync(struct amd_iommu *iommu, u16 devid);
86 static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid);
91 static void clone_aliases(struct amd_iommu *iommu, struct device *dev);
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| /linux/tools/testing/selftests/vfio/lib/ |
| H A D | iommu.c | 39 .container_path = "/dev/iommu",
44 .container_path = "/dev/iommu",
66 VFIO_FAIL("Unrecognized IOMMU mode: %s\n", iommu_mode); in lookup_iommu_mode()
69 int __iommu_hva2iova(struct iommu *iommu, void *vaddr, iova_t *iova) in __iommu_hva2iova() argument
73 list_for_each_entry(region, &iommu->dma_regions, link) { in __iommu_hva2iova()
89 iova_t iommu_hva2iova(struct iommu *iommu, void *vaddr) in iommu_hva2iova() argument
94 ret = __iommu_hva2iova(iommu, vaddr, &iova); in iommu_hva2iova()
95 VFIO_ASSERT_EQ(ret, 0, "%p is not mapped into the iommu\n", vaddr); in iommu_hva2iova()
100 static int vfio_iommu_map(struct iommu *iommu, struct dma_region *region) in vfio_iommu_map() argument
110 if (ioctl(iommu->container_fd, VFIO_IOMMU_MAP_DMA, &args)) in vfio_iommu_map()
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| /linux/Documentation/devicetree/bindings/iommu/ |
| H A D | iommu.txt | 5 IOMMU device node:
8 An IOMMU can provide the following services:
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
36 1:1 mapping from IOMMU to memory.
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
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| H A D | qcom,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
14 a similar looking IOMMU, but without access to the global register space
23 - qcom,msm8916-iommu
24 - qcom,msm8917-iommu
25 - qcom,msm8937-iommu
26 - qcom,msm8953-iommu
27 - const: qcom,msm-iommu-v1
30 - qcom,msm8953-iommu
31 - qcom,msm8976-iommu
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| H A D | mediatek,iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/mediatek,iommu.yaml#
7 title: MediaTek IOMMU Architecture Implementation
77 - mediatek,mt6893-iommu-mm # generation two
81 - mediatek,mt8186-iommu-mm # generation two
82 - mediatek,mt8188-iommu-vdo # generation two
83 - mediatek,mt8188-iommu-vpp # generation two
84 - mediatek,mt8188-iommu-infra # generation two
85 - mediatek,mt8189-iommu-apu # generation two
86 - mediatek,mt8189-iommu-infra # generation two
87 - mediatek,mt8189-iommu-mm # generation two
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| H A D | sprd,iommu.yaml | 5 $id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
8 title: Unisoc IOMMU and Multi-media MMU
16 - sprd,iommu-v1
18 "#iommu-cells":
21 Unisoc IOMMUs are all single-master IOMMU devices, therefore no
24 Documentation/devicetree/bindings/iommu/iommu.txt
37 - "#iommu-cells"
43 iommu_disp: iommu@63000800 {
44 compatible = "sprd,iommu-v1";
46 #iommu-cells = <0>;
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| H A D | allwinner,sun50i-h6-iommu.yaml | 4 $id: http://devicetree.org/schemas/iommu/allwinner,sun50i-h6-iommu.yaml#
7 title: Allwinner H6 IOMMU
14 "#iommu-cells":
21 - const: allwinner,sun50i-h6-iommu
22 - const: allwinner,sun50i-h616-iommu
24 - const: allwinner,sun55i-a523-iommu
25 - const: allwinner,sun50i-h616-iommu
40 - "#iommu-cells"
57 iommu: iommu@30f0000 {
58 compatible = "allwinner,sun50i-h6-iommu";
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| H A D | qcom,apq8064-iommu.yaml | 5 $id: http://devicetree.org/schemas/iommu/qcom,apq8064-iommu.yaml#
8 title: Qualcomm APQ8064 IOMMU
14 The MSM IOMMU is an implementation compatible with the ARM VMSA short
16 outside of the CPU, each connected to the IOMMU through a port called micro-TLB.
20 const: qcom,apq8064-iommu
42 "#iommu-cells":
44 description: Each IOMMU specifier describes a single Stream ID.
48 description: The total number of context banks in the IOMMU.
67 iommu@7500000 {
68 compatible = "qcom,apq8064-iommu";
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| /linux/tools/testing/selftests/vfio/lib/include/libvfio/ |
| H A D | iommu.h | 27 struct iommu { struct
35 struct iommu *iommu_init(const char *iommu_mode); argument
36 void iommu_cleanup(struct iommu *iommu);
38 int __iommu_map(struct iommu *iommu, struct dma_region *region);
40 static inline void iommu_map(struct iommu *iommu, struct dma_region *region) in iommu_map() argument
42 VFIO_ASSERT_EQ(__iommu_map(iommu, region), 0); in iommu_map()
45 int __iommu_unmap(struct iommu *iomm
28 modeiommu global() argument
30 iommufdiommu global() argument
47 iommu_unmap(struct iommu * iommu,struct dma_region * region) iommu_unmap() argument
54 iommu_unmap_all(struct iommu * iommu) iommu_unmap_all() argument
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| /linux/Documentation/ABI/testing/ |
| H A D | debugfs-amd-iommu | 1 What: /sys/kernel/debug/iommu/amd/iommu<x>/mmio
6 MMIO register offset for iommu<x>, and the file outputs the corresponding
7 MMIO register value of iommu<x>
11 $ echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio
12 $ cat /sys/kernel/debug/iommu/amd/iommu00/mmio
18 What: /sys/kernel/debug/iommu/amd/iommu<x>/capability
23 capability register offset for iommu<x>, and the file outputs the
24 corresponding capability register value of iommu<x>.
28 $ echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability
29 $ cat /sys/kernel/debug/iommu/amd/iommu00/capability
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| H A D | debugfs-intel-iommu | 1 What: /sys/kernel/debug/iommu/intel/iommu_regset
5 This file dumps all the register contents for each IOMMU device.
11 $ sudo cat /sys/kernel/debug/iommu/intel/iommu_regset
13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
46 What: /sys/kernel/debug/iommu/intel/ir_translation_struct
57 $ sudo cat /sys/kernel/debug/iommu/intel/ir_translation_struct
59 Remapped Interrupt supported on IOMMU: dmar0
66 Remapped Interrupt supported on IOMMU: dmar1
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| H A D | sysfs-class-iommu-intel-iommu | 1 What: /sys/class/iommu/<iommu>/intel-iommu/address
6 Physical address of the VT-d DRHD for this IOMMU.
8 intel-iommu with a DMAR DRHD table entry.
10 What: /sys/class/iommu/<iommu>/intel-iommu/cap
18 What: /sys/class/iommu/<iommu>/intel-iommu/ecap
26 What: /sys/class/iommu/<iommu>/intel-iommu/version
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| /linux/arch/sparc/mm/ |
| H A D | iommu.c | 3 * iommu.c: IOMMU specific routines for memory management.
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
67 iommu = kmalloc_obj(struct iommu_struct); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
75 if (!iommu->regs) { in sbus_iommu_init()
76 prom_printf("Cannot map IOMMU registers\n"); in sbus_iommu_init()
80 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
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| /linux/Documentation/devicetree/bindings/virtio/ |
| H A D | pci-iommu.yaml | 4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
7 title: virtio-iommu device using the virtio-pci transport
13 When virtio-iommu uses the PCI transport, its programming interface is
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
17 contains a child node representing the IOMMU device explicitly.
19 DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
20 virtio-iommu node doesn't have an "iommus" property, and is omitted from
21 the iommu-map property of the root complex.
33 - const: virtio,pci-iommu
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| /linux/drivers/iommu/intel/ |
| H A D | svm.c | 22 #include "iommu.h"
25 #include "../iommu-pages.h"
28 void intel_svm_check(struct intel_iommu *iommu) in intel_svm_check() argument
30 if (!pasid_supported(iommu) || !ecap_smpwc(iommu->ecap)) in intel_svm_check()
34 !cap_fl1gp_support(iommu->cap)) { in intel_svm_check()
36 iommu->name); in intel_svm_check()
41 !cap_fl5lp_support(iommu->cap)) { in intel_svm_check()
43 iommu->name); in intel_svm_check()
47 iommu->flags |= VTD_FLAG_SVM_CAPABLE; in intel_svm_check()
64 * different from IOMMU subsystem using the last address of an address in intel_arch_invalidate_secondary_tlbs()
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| H A D | perf.c | 13 #include "iommu.h"
18 bool dmar_latency_enabled(struct intel_iommu *iommu, enum latency_type type) in dmar_latency_enabled() argument
20 struct latency_statistic *lstat = iommu->perf_statistic; in dmar_latency_enabled()
25 int dmar_latency_enable(struct intel_iommu *iommu, enum latency_type type) in dmar_latency_enable() argument
31 if (dmar_latency_enabled(iommu, type)) in dmar_latency_enable()
35 if (!iommu->perf_statistic) { in dmar_latency_enable()
36 iommu->perf_statistic = kzalloc_objs(*lstat, DMAR_LATENCY_NUM, in dmar_latency_enable()
38 if (!iommu->perf_statistic) { in dmar_latency_enable()
44 lstat = iommu->perf_statistic; in dmar_latency_enable()
57 void dmar_latency_disable(struct intel_iommu *iommu, enum latency_type type) in dmar_latency_disable() argument
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| H A D | nested.c | 14 #include <linux/iommu.h>
18 #include "iommu.h"
26 struct intel_iommu *iommu = info->iommu; in intel_nested_attach_dev() local
35 * to ensure the s2_domain is compatible with this IOMMU. in intel_nested_attach_dev()
43 ret = domain_attach_iommu(dmar_domain, iommu); in intel_nested_attach_dev()
45 dev_err_ratelimited(dev, "Failed to attach domain to iommu\n"); in intel_nested_attach_dev()
57 ret = intel_pasid_setup_nested(iommu, dev, in intel_nested_attach_dev()
74 domain_detach_iommu(dmar_domain, iommu); in intel_nested_attach_dev()
134 static int domain_setup_nested(struct intel_iommu *iommu, in domain_setup_nested() argument
140 intel_pasid_tear_down_entry(iommu, dev, pasid, false); in domain_setup_nested()
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