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/linux/arch/sparc/kernel/
H A Diommu.c2 /* iommu.c: Generic sparc64 IOMMU support.
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
49 /* Must be invoked under the IOMMU lock. */
52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
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H A Diommu-common.c3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
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/linux/drivers/iommu/
H A Dsun50i-iommu.c14 #include <linux/iommu.h>
29 #include "iommu-pages.h"
101 struct iommu_device iommu; member
103 /* Lock to modify the IOMMU registers */
125 struct sun50i_iommu *iommu; member
138 static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) in iommu_read() argument
140 return readl(iommu->base + offset); in iommu_read()
143 static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value) in iommu_write() argument
145 writel(value, iommu->base + offset); in iommu_write()
149 * The Allwinner H6 IOMMU uses a 2-level page table.
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H A Dmsm_iommu.c18 #include <linux/iommu.h>
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
71 static void __disable_clocks(struct msm_iommu_dev *iommu) in __disable_clocks() argument
73 if (iommu->clk) in __disable_clocks()
74 clk_disable(iommu->clk); in __disable_clocks()
75 clk_disable(iommu->pclk); in __disable_clocks()
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H A Drockchip-iommu.c3 * IOMMU API for Rockchip
17 #include <linux/iommu.h>
30 #include "iommu-pages.h"
96 /* list of clocks required by IOMMU */
117 struct iommu_device iommu; member
119 struct iommu_domain *domain; /* domain to which iommu is attached */
123 struct device_link *link; /* runtime PM link from IOMMU to master */
124 struct rk_iommu *iommu; member
144 * The Rockchip rk3288 iommu uses a 2-level page table.
153 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
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H A DKconfig15 bool "IOMMU Hardware Support"
26 menu "Generic IOMMU Pagetable Support"
60 for 64KB pages/16MB supersections if indicated by the IOMMU driver.
86 bool "Export IOMMU internals in DebugFS"
89 Allows exposure of IOMMU device internals. This option enables
90 the use of debugfs by IOMMU drivers as required. Devices can,
91 at initialization time, cause the IOMMU code to create a top-level
92 debug/iommu directory, and then populate a subdirectory with
96 prompt "IOMMU default domain type"
101 Choose the type of IOMMU domain used to manage DMA API usage by
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H A DMakefile6 obj-$(CONFIG_IOMMU_API) += iommu.o
7 obj-$(CONFIG_IOMMU_SUPPORT) += iommu-pages.o
8 obj-$(CONFIG_IOMMU_API) += iommu-traces.o
9 obj-$(CONFIG_IOMMU_API) += iommu-sysfs.o
10 obj-$(CONFIG_IOMMU_DEBUGFS) += iommu-debugfs.o
11 obj-$(CONFIG_IOMMU_DMA) += dma-iommu.o
23 obj-$(CONFIG_OMAP_IOMMU) += omap-iommu.o
24 obj-$(CONFIG_OMAP_IOMMU_DEBUG) += omap-iommu-debug.o
25 obj-$(CONFIG_ROCKCHIP_IOMMU) += rockchip-iommu.o
26 obj-$(CONFIG_SUN50I_IOMMU) += sun50i-iommu.o
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/linux/drivers/iommu/intel/
H A Dpasid.c15 #include <linux/iommu.h>
21 #include "iommu.h"
23 #include "../iommu-pages.h"
26 * Intel IOMMU system wide PASID name space:
63 dir = iommu_alloc_pages_node_sz(info->iommu->node, GFP_KERNEL, in intel_pasid_alloc_table()
74 if (!ecap_coherent(info->iommu->ecap)) in intel_pasid_alloc_table()
151 entries = iommu_alloc_pages_node_sz(info->iommu->node, in intel_pasid_get_entry()
168 if (!ecap_coherent(info->iommu->ecap)) { in intel_pasid_get_entry()
196 pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, in pasid_cache_invalidation_with_pasid() argument
207 qi_submit_sync(iommu, &desc, 1, 0); in pasid_cache_invalidation_with_pasid()
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H A Dirq_remapping.c25 #include "iommu.h"
27 #include "../iommu-pages.h"
30 struct intel_iommu *iommu; member
37 struct intel_iommu *iommu; member
44 struct intel_iommu *iommu; member
72 * ->iommu->register_lock
81 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
85 static bool ir_pre_enabled(struct intel_iommu *iommu) in ir_pre_enabled() argument
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); in ir_pre_enabled()
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu) in clear_ir_pre_enabled() argument
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H A Ddmar.c28 #include <linux/iommu.h>
33 #include "iommu.h"
35 #include "../iommu-pages.h"
68 static void free_iommu(struct intel_iommu *iommu);
462 if (dmaru->iommu) in dmar_free_drhd()
463 free_iommu(dmaru->iommu); in dmar_free_drhd()
502 drhd->iommu->node = node; in dmar_parse_one_rhsa()
767 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
939 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
950 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
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H A Dcache.c13 #include <linux/iommu.h>
18 #include "iommu.h"
24 struct intel_iommu *iommu, struct device *dev, in cache_tage_match() argument
34 return tag->iommu == iommu; in cache_tage_match()
47 struct intel_iommu *iommu = info->iommu; in cache_tag_assign() local
57 tag->iommu = iommu; in cache_tag_assign()
65 tag->dev = iommu->iommu.dev; in cache_tag_assign()
70 if (cache_tage_match(temp, did, iommu, dev, pasid, type)) { in cache_tag_assign()
77 if (temp->iommu == iommu) in cache_tag_assign()
81 * Link cache tags of same iommu unit together, so corresponding in cache_tag_assign()
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H A Dperfmon.c3 * Support Intel IOMMU PerfMon
10 #include "iommu.h"
327 struct intel_iommu *iommu = iommu_pmu->iommu; in iommu_pmu_start() local
349 * Only IOMMU PMU returns runtime HW error. We don't want to in iommu_pmu_start()
356 ecmd_submit_sync(iommu, DMA_ECMD_ENABLE, hwc->idx, 0); in iommu_pmu_start()
364 struct intel_iommu *iommu = iommu_pmu->iommu; in iommu_pmu_stop() local
368 ecmd_submit_sync(iommu, DMA_ECMD_DISABLE, hwc->idx, 0); in iommu_pmu_stop()
476 struct intel_iommu *iommu = iommu_pmu->iommu; in iommu_pmu_enable() local
478 ecmd_submit_sync(iommu, DMA_ECMD_UNFREEZE, 0, 0); in iommu_pmu_enable()
484 struct intel_iommu *iommu = iommu_pmu->iommu; in iommu_pmu_disable() local
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/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
7 title: RISC-V IOMMU Architecture Implementation
13 The RISC-V IOMMU provides memory address translation and isolation for
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
24 For information on assigning RISC-V IOMMU to its peripheral devices,
25 see generic IOMMU bindings.
28 # For PCIe IOMMU hardware compatible property should contain the vendor
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
37 - qemu,riscv-iommu
38 - const: riscv,iommu
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H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
36 1:1 mapping from IOMMU to memory.
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
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H A Dqcom,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
14 a similar looking IOMMU, but without access to the global register space
23 - qcom,msm8916-iommu
24 - qcom,msm8917-iommu
25 - qcom,msm8937-iommu
26 - qcom,msm8953-iommu
27 - const: qcom,msm-iommu-v1
30 - qcom,msm8953-iommu
31 - qcom,msm8976-iommu
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H A Dti,omap-iommu.txt1 OMAP2+ IOMMU
5 "ti,omap2-iommu" for OMAP2/OMAP3 IOMMU instances
6 "ti,omap4-iommu" for OMAP4/OMAP5 IOMMU instances
7 "ti,dra7-dsp-iommu" for DRA7xx DSP IOMMU instances
8 "ti,dra7-iommu" for DRA7xx IOMMU instances
9 - ti,hwmods : Name of the hwmod associated with the IOMMU instance
11 - interrupts : Interrupt specifier for the IOMMU instance
12 - #iommu-cells : Should be 0. OMAP IOMMUs are all "single-master" devices,
16 Documentation/devicetree/bindings/iommu/iommu.txt
21 - ti,iommu-bus-err-back : Indicates the IOMMU instance supports throwing
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H A Dsprd,iommu.yaml5 $id: http://devicetree.org/schemas/iommu/sprd,iommu.yaml#
8 title: Unisoc IOMMU and Multi-media MMU
16 - sprd,iommu-v1
18 "#iommu-cells":
21 Unisoc IOMMUs are all single-master IOMMU devices, therefore no
24 Documentation/devicetree/bindings/iommu/iommu.txt
37 - "#iommu-cells"
43 iommu_disp: iommu@63000800 {
44 compatible = "sprd,iommu-v1";
46 #iommu-cells = <0>;
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/linux/drivers/iommu/amd/
H A Dppr.c9 #include <linux/amd-iommu.h>
13 #include <asm/iommu.h>
18 #include "../iommu-pages.h"
20 int __init amd_iommu_alloc_ppr_log(struct amd_iommu *iommu) in amd_iommu_alloc_ppr_log() argument
22 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in amd_iommu_alloc_ppr_log()
24 return iommu->ppr_log ? 0 : -ENOMEM; in amd_iommu_alloc_ppr_log()
27 void amd_iommu_enable_ppr_log(struct amd_iommu *iommu) in amd_iommu_enable_ppr_log() argument
31 if (iommu->ppr_log == NULL) in amd_iommu_enable_ppr_log()
34 iommu_feature_enable(iommu, CONTROL_PPR_EN); in amd_iommu_enable_ppr_log()
36 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in amd_iommu_enable_ppr_log()
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H A Ddebugfs.c3 * AMD IOMMU driver
28 struct amd_iommu *iommu = m->private; in iommu_mmio_write() local
31 iommu->dbg_mmio_offset = -1; in iommu_mmio_write()
36 ret = kstrtou32_from_user(ubuf, cnt, 0, &iommu->dbg_mmio_offset); in iommu_mmio_write()
40 if (iommu->dbg_mmio_offset > iommu->mmio_phys_end - 4) { in iommu_mmio_write()
41 iommu->dbg_mmio_offset = -1; in iommu_mmio_write()
50 struct amd_iommu *iommu = m->private; in iommu_mmio_show() local
53 if (iommu->dbg_mmio_offset < 0) { in iommu_mmio_show()
58 value = readq(iommu->mmio_base + iommu->dbg_mmio_offset); in iommu_mmio_show()
59 seq_printf(m, "Offset:0x%x Value:0x%016llx\n", iommu->dbg_mmio_offset, value); in iommu_mmio_show()
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H A Damd_iommu.h10 #include <linux/iommu.h>
19 void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type,
22 void amd_iommu_restart_event_logging(struct amd_iommu *iommu);
23 void amd_iommu_restart_ga_log(struct amd_iommu *iommu);
24 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu);
25 void amd_iommu_set_rlookup_table(struct amd_iommu *iommu, u16 devid);
26 void iommu_feature_enable(struct amd_iommu *iommu, u8 bit);
27 void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
65 int amd_iommu_iopf_init(struct amd_iommu *iommu);
66 void amd_iommu_iopf_uninit(struct amd_iommu *iommu);
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/linux/Documentation/ABI/testing/
H A Ddebugfs-amd-iommu1 What: /sys/kernel/debug/iommu/amd/iommu<x>/mmio
6 MMIO register offset for iommu<x>, and the file outputs the corresponding
7 MMIO register value of iommu<x>
11 $ echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio
12 $ cat /sys/kernel/debug/iommu/amd/iommu00/mmio
18 What: /sys/kernel/debug/iommu/amd/iommu<x>/capability
23 capability register offset for iommu<x>, and the file outputs the
24 corresponding capability register value of iommu<x>.
28 $ echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability
29 $ cat /sys/kernel/debug/iommu/amd/iommu00/capability
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H A Ddebugfs-intel-iommu1 What: /sys/kernel/debug/iommu/intel/iommu_regset
5 This file dumps all the register contents for each IOMMU device.
11 $ sudo cat /sys/kernel/debug/iommu/intel/iommu_regset
13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
46 What: /sys/kernel/debug/iommu/intel/ir_translation_struct
57 $ sudo cat /sys/kernel/debug/iommu/intel/ir_translation_struct
59 Remapped Interrupt supported on IOMMU: dmar0
66 Remapped Interrupt supported on IOMMU: dmar1
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H A Dsysfs-class-iommu-intel-iommu1 What: /sys/class/iommu/<iommu>/intel-iommu/address
6 Physical address of the VT-d DRHD for this IOMMU.
8 intel-iommu with a DMAR DRHD table entry.
10 What: /sys/class/iommu/<iommu>/intel-iommu/cap
18 What: /sys/class/iommu/<iommu>/intel-iommu/ecap
26 What: /sys/class/iommu/<iommu>/intel-iommu/version
/linux/arch/sparc/mm/
H A Diommu.c3 * iommu.c: IOMMU specific routines for memory management.
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
67 iommu = kmalloc(sizeof(struct iommu_struct), GFP_KERNEL); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
75 if (!iommu->regs) { in sbus_iommu_init()
76 prom_printf("Cannot map IOMMU registers\n"); in sbus_iommu_init()
80 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
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/linux/Documentation/devicetree/bindings/virtio/
H A Dpci-iommu.yaml4 $id: http://devicetree.org/schemas/virtio/pci-iommu.yaml#
7 title: virtio-iommu device using the virtio-pci transport
13 When virtio-iommu uses the PCI transport, its programming interface is
15 device tree statically describes the relation between IOMMU and DMA
16 masters. Therefore, the PCI root complex that hosts the virtio-iommu
17 contains a child node representing the IOMMU device explicitly.
19 DMA from the IOMMU device isn't managed by another IOMMU. Therefore the
20 virtio-iommu node doesn't have an "iommus" property, and is omitted from
21 the iommu-map property of the root complex.
33 - const: virtio,pci-iommu
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