Home
last modified time | relevance | path

Searched full:iommu (Results 1 – 25 of 688) sorted by relevance

12345678910>>...28

/linux/arch/sparc/kernel/
H A Diommu.c2 /* iommu.c: Generic sparc64 IOMMU support.
15 #include <linux/iommu-helper.h>
17 #include <asm/iommu-common.h>
23 #include <asm/iommu.h>
49 /* Must be invoked under the IOMMU lock. */
52 struct iommu *iommu = container_of(iommu_map_table, struct iommu, tbl); in iommu_flushall() local
53 if (iommu->iommu_flushinv) { in iommu_flushall()
54 iommu_write(iommu->iommu_flushinv, ~(u64)0); in iommu_flushall()
59 tag = iommu->iommu_tags; in iommu_flushall()
66 (void) iommu_read(iommu->write_complete_reg); in iommu_flushall()
[all …]
H A Diommu-common.c3 * IOMMU mmap management and range allocation functions.
4 * Based almost entirely upon the powerpc iommu allocator.
10 #include <linux/iommu-helper.h>
13 #include <asm/iommu-common.h>
19 static inline bool need_flush(struct iommu_map_table *iommu) in need_flush() argument
21 return ((iommu->flags & IOMMU_NEED_FLUSH) != 0); in need_flush()
24 static inline void set_flush(struct iommu_map_table *iommu) in set_flush() argument
26 iommu->flags |= IOMMU_NEED_FLUSH; in set_flush()
29 static inline void clear_flush(struct iommu_map_table *iommu) in clear_flush() argument
31 iommu->flags &= ~IOMMU_NEED_FLUSH; in clear_flush()
[all …]
/linux/drivers/iommu/
H A Dsun50i-iommu.c14 #include <linux/iommu.h>
29 #include "iommu-pages.h"
101 struct iommu_device iommu; member
103 /* Lock to modify the IOMMU registers */
125 struct sun50i_iommu *iommu; member
138 static u32 iommu_read(struct sun50i_iommu *iommu, u32 offset) in iommu_read() argument
140 return readl(iommu->base + offset); in iommu_read()
143 static void iommu_write(struct sun50i_iommu *iommu, u32 offset, u32 value) in iommu_write() argument
145 writel(value, iommu->base + offset); in iommu_write()
149 * The Allwinner H6 IOMMU uses a 2-level page table.
[all …]
H A Dmsm_iommu.c18 #include <linux/iommu.h>
54 static int __enable_clocks(struct msm_iommu_dev *iommu) in __enable_clocks() argument
58 ret = clk_enable(iommu->pclk); in __enable_clocks()
62 if (iommu->clk) { in __enable_clocks()
63 ret = clk_enable(iommu->clk); in __enable_clocks()
65 clk_disable(iommu->pclk); in __enable_clocks()
71 static void __disable_clocks(struct msm_iommu_dev *iommu) in __disable_clocks() argument
73 if (iommu->clk) in __disable_clocks()
74 clk_disable(iommu->clk); in __disable_clocks()
75 clk_disable(iommu->pclk); in __disable_clocks()
[all …]
H A Drockchip-iommu.c3 * IOMMU API for Rockchip
17 #include <linux/iommu.h>
30 #include "iommu-pages.h"
96 /* list of clocks required by IOMMU */
117 struct iommu_device iommu; member
119 struct iommu_domain *domain; /* domain to which iommu is attached */
123 struct device_link *link; /* runtime PM link from IOMMU to master */
124 struct rk_iommu *iommu; member
144 * The Rockchip rk3288 iommu uses a 2-level page table.
153 * Each iommu device has a MMU_DTE_ADDR register that contains the physical
[all …]
H A Diommu-sysfs.c3 * IOMMU sysfs class support
10 #include <linux/iommu.h>
16 * As devices are added to the IOMMU, we'll add links to the group.
38 .name = "iommu",
50 * Init the struct device for the IOMMU. IOMMU specific attributes can
52 * IOMMU type.
54 int iommu_device_sysfs_add(struct iommu_device *iommu, in iommu_device_sysfs_add() argument
62 iommu->dev = kzalloc_obj(*iommu->dev); in iommu_device_sysfs_add()
63 if (!iommu->dev) in iommu_device_sysfs_add()
66 device_initialize(iommu->dev); in iommu_device_sysfs_add()
[all …]
/linux/drivers/iommu/amd/
H A Dinit.c19 #include <linux/amd-iommu.h>
25 #include <asm/iommu.h>
38 #include "../iommu-pages.h"
98 * structure describing one IOMMU in the ACPI table. Typically followed by one
118 * A device entry describing which devices a specific IOMMU translates and
136 * An AMD IOMMU memory definition structure. It defines things like exclusion
232 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
234 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
237 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
239 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
[all …]
H A Dppr.c9 #include <linux/amd-iommu.h>
13 #include <asm/iommu.h>
18 #include "../iommu-pages.h"
20 int __init amd_iommu_alloc_ppr_log(struct amd_iommu *iommu) in amd_iommu_alloc_ppr_log() argument
22 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in amd_iommu_alloc_ppr_log()
24 return iommu->ppr_log ? 0 : -ENOMEM; in amd_iommu_alloc_ppr_log()
27 void amd_iommu_enable_ppr_log(struct amd_iommu *iommu) in amd_iommu_enable_ppr_log() argument
31 if (iommu->ppr_log == NULL) in amd_iommu_enable_ppr_log()
34 iommu_feature_enable(iommu, CONTROL_PPR_EN); in amd_iommu_enable_ppr_log()
36 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in amd_iommu_enable_ppr_log()
[all …]
H A Ddebugfs.c3 * AMD IOMMU driver
28 struct amd_iommu *iommu = m->private; in iommu_mmio_write() local
31 iommu->dbg_mmio_offset = -1; in iommu_mmio_write()
36 ret = kstrtou32_from_user(ubuf, cnt, 0, &iommu->dbg_mmio_offset); in iommu_mmio_write()
40 if (iommu->dbg_mmio_offset > iommu->mmio_phys_end - sizeof(u64)) { in iommu_mmio_write()
41 iommu->dbg_mmio_offset = -1; in iommu_mmio_write()
50 struct amd_iommu *iommu = m->private; in iommu_mmio_show() local
53 if (iommu->dbg_mmio_offset < 0) { in iommu_mmio_show()
58 value = readq(iommu->mmio_base + iommu->dbg_mmio_offset); in iommu_mmio_show()
59 seq_printf(m, "Offset:0x%x Value:0x%016llx\n", iommu->dbg_mmio_offset, value); in iommu_mmio_show()
[all …]
H A Diommu.c23 #include <linux/iommu-helper.h>
25 #include <linux/amd-iommu.h>
39 #include <asm/iommu.h>
43 #include <linux/generic_pt/iommu.h>
48 #include "../iommu-pages.h"
67 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
75 static void set_dte_entry(struct amd_iommu *iommu,
84 static void iommu_flush_dte_sync(struct amd_iommu *iommu, u16 devid);
86 static struct iommu_dev_data *find_dev_data(struct amd_iommu *iommu, u16 devid);
91 static void clone_aliases(struct amd_iommu *iommu, struct device *dev);
[all …]
/linux/drivers/iommu/intel/
H A Diommu.c27 #include "iommu.h"
28 #include "../dma-iommu.h"
30 #include "../iommu-pages.h"
53 #define rwbf_required(iommu) (rwbf_quirk || cap_rwbf((iommu)->cap)) argument
114 * Looks up an IOMMU-probed device using its source ID.
120 * released by the iommu subsystem after being returned. The caller
124 struct device *device_rbtree_find(struct intel_iommu *iommu, u16 rid) in device_rbtree_find() argument
130 spin_lock_irqsave(&iommu->device_rbtree_lock, flags); in device_rbtree_find()
131 node = rb_find(&rid, &iommu->device_rbtree, device_rid_cmp_key); in device_rbtree_find()
134 spin_unlock_irqrestore(&iommu->device_rbtree_lock, flags); in device_rbtree_find()
[all …]
H A Dirq_remapping.c25 #include "iommu.h"
27 #include "../iommu-pages.h"
30 struct intel_iommu *iommu; member
37 struct intel_iommu *iommu; member
44 struct intel_iommu *iommu; member
72 * ->iommu->register_lock
81 static void iommu_disable_irq_remapping(struct intel_iommu *iommu);
85 static bool ir_pre_enabled(struct intel_iommu *iommu) in ir_pre_enabled() argument
87 return (iommu->flags & VTD_FLAG_IRQ_REMAP_PRE_ENABLED); in ir_pre_enabled()
90 static void clear_ir_pre_enabled(struct intel_iommu *iommu) in clear_ir_pre_enabled() argument
[all …]
H A Dpasid.c15 #include <linux/iommu.h>
21 #include "iommu.h"
23 #include "../iommu-pages.h"
26 * Intel IOMMU system wide PASID name space:
63 dir = iommu_alloc_pages_node_sz(info->iommu->node, GFP_KERNEL, in intel_pasid_alloc_table()
74 if (!ecap_coherent(info->iommu->ecap)) in intel_pasid_alloc_table()
151 entries = iommu_alloc_pages_node_sz(info->iommu->node, in intel_pasid_get_entry()
156 if (!ecap_coherent(info->iommu->ecap)) in intel_pasid_get_entry()
171 if (!ecap_coherent(info->iommu->ecap)) in intel_pasid_get_entry()
197 pasid_cache_invalidation_with_pasid(struct intel_iommu *iommu, in pasid_cache_invalidation_with_pasid() argument
[all …]
H A Ddmar.c28 #include <linux/iommu.h>
33 #include "iommu.h"
35 #include "../iommu-pages.h"
68 static void free_iommu(struct intel_iommu *iommu);
462 if (dmaru->iommu) in dmar_free_drhd()
463 free_iommu(dmaru->iommu); in dmar_free_drhd()
502 drhd->iommu->node = node; in dmar_parse_one_rhsa()
767 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
939 x86_init.iommu.iommu_init = intel_iommu_init; in detect_intel_iommu()
950 static void unmap_iommu(struct intel_iommu *iommu) in unmap_iommu() argument
[all …]
H A Dcache.c13 #include <linux/iommu.h>
18 #include "iommu.h"
24 struct intel_iommu *iommu, struct device *dev, in cache_tage_match() argument
34 return tag->iommu == iommu; in cache_tage_match()
47 struct intel_iommu *iommu = info->iommu; in cache_tag_assign() local
57 tag->iommu = iommu; in cache_tag_assign()
65 tag->dev = iommu->iommu.dev; in cache_tag_assign()
70 if (cache_tage_match(temp, did, iommu, dev, pasid, type)) { in cache_tag_assign()
77 if (temp->iommu == iommu) in cache_tag_assign()
81 * Link cache tags of same iommu unit together, so corresponding in cache_tag_assign()
[all …]
/linux/tools/testing/selftests/vfio/lib/
H A Diommu.c39 .container_path = "/dev/iommu",
44 .container_path = "/dev/iommu",
66 VFIO_FAIL("Unrecognized IOMMU mode: %s\n", iommu_mode); in lookup_iommu_mode()
69 int __iommu_hva2iova(struct iommu *iommu, void *vaddr, iova_t *iova) in __iommu_hva2iova() argument
73 list_for_each_entry(region, &iommu->dma_regions, link) { in __iommu_hva2iova()
89 iova_t iommu_hva2iova(struct iommu *iommu, void *vaddr) in iommu_hva2iova() argument
94 ret = __iommu_hva2iova(iommu, vaddr, &iova); in iommu_hva2iova()
95 VFIO_ASSERT_EQ(ret, 0, "%p is not mapped into the iommu\n", vaddr); in iommu_hva2iova()
100 static int vfio_iommu_map(struct iommu *iommu, struct dma_region *region) in vfio_iommu_map() argument
110 if (ioctl(iommu->container_fd, VFIO_IOMMU_MAP_DMA, &args)) in vfio_iommu_map()
[all …]
/linux/drivers/iommu/riscv/
H A Diommu.c3 * IOMMU API for RISC-V IOMMU implementations.
13 #define pr_fmt(fmt) "riscv-iommu: " fmt
20 #include <linux/iommu.h>
25 #include "../iommu-pages.h"
26 #include "iommu-bits.h"
27 #include "iommu.h"
39 /* RISC-V IOMMU PPN <> PHYS address conversions, PHYS <=> PPN[53:10] */
44 iommu_get_iommu_dev(dev, struct riscv_iommu_device, iommu)
46 /* IOMMU PSCID allocation namespace. */
70 static void *riscv_iommu_get_pages(struct riscv_iommu_device *iommu, in riscv_iommu_get_pages() argument
[all …]
/linux/Documentation/devicetree/bindings/iommu/
H A Driscv,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/riscv,iommu.yaml#
7 title: RISC-V IOMMU Architecture Implementation
13 The RISC-V IOMMU provides memory address translation and isolation for
22 Visit https://github.com/riscv-non-isa/riscv-iommu for more details.
24 For information on assigning RISC-V IOMMU to its peripheral devices,
25 see generic IOMMU bindings.
28 # For PCIe IOMMU hardware compatible property should contain the vendor
31 # actually required. For non-PCIe hardware implementations 'riscv,iommu'
37 - qemu,riscv-iommu
38 - const: riscv,iommu
[all …]
H A Diommu.txt5 IOMMU device node:
8 An IOMMU can provide the following services:
19 through the IOMMU and faulting when encountering accesses to unmapped
29 IOMMUs can be single-master or multiple-master. Single-master IOMMU devices
31 master IOMMU devices can translate accesses from more than one master.
33 The device tree node of the IOMMU device's parent bus must contain a valid
35 IOMMU maps to memory. An empty "dma-ranges" property means that there is a
36 1:1 mapping from IOMMU to memory.
40 - #iommu-cells: The number of cells in an IOMMU specifier needed to encode an
43 The meaning of the IOMMU specifier is defined by the device tree binding of
[all …]
H A Dqcom,iommu.yaml4 $id: http://devicetree.org/schemas/iommu/qcom,iommu.yaml#
7 title: Qualcomm Technologies legacy IOMMU implementations
14 a similar looking IOMMU, but without access to the global register space
23 - qcom,msm8916-iommu
24 - qcom,msm8917-iommu
25 - qcom,msm8937-iommu
26 - qcom,msm8953-iommu
27 - const: qcom,msm-iommu-v1
30 - qcom,msm8953-iommu
31 - qcom,msm8976-iommu
[all …]
/linux/drivers/vfio/
H A Dvfio_iommu_type1.c3 * VFIO: IOMMU DMA mapping support for Type1 IOMMU
12 * We arbitrarily define a Type1 IOMMU as one matching the below code.
13 * It could be called the x86 IOMMU as it's designed for AMD-Vi & Intel
15 * implementing a similar IOMMU could make use of this. We expect the
16 * IOMMU to support the IOMMU API and have few to no restrictions around
17 * the IOVA range that can be mapped. The Type1 IOMMU is currently
19 * userspace pages pinned into memory. We also assume devices and IOMMU
20 * domains are PCI based as the IOMMU API is still centered around a
28 #include <linux/iommu.h>
46 #define DRIVER_DESC "Type1 IOMMU driver for VFIO"
[all …]
/linux/tools/testing/selftests/vfio/lib/include/libvfio/
H A Diommu.h27 struct iommu { struct
35 struct iommu *iommu_init(const char *iommu_mode); argument
36 void iommu_cleanup(struct iommu *iommu);
38 int __iommu_map(struct iommu *iommu, struct dma_region *region);
40 static inline void iommu_map(struct iommu *iommu, struct dma_region *region) in iommu_map() argument
42 VFIO_ASSERT_EQ(__iommu_map(iommu, region), 0); in iommu_map()
45 int __iommu_unmap(struct iommu *iomm
28 modeiommu global() argument
30 iommufdiommu global() argument
47 iommu_unmap(struct iommu * iommu,struct dma_region * region) iommu_unmap() argument
54 iommu_unmap_all(struct iommu * iommu) iommu_unmap_all() argument
[all...]
/linux/Documentation/ABI/testing/
H A Ddebugfs-amd-iommu1 What: /sys/kernel/debug/iommu/amd/iommu<x>/mmio
6 MMIO register offset for iommu<x>, and the file outputs the corresponding
7 MMIO register value of iommu<x>
11 $ echo "0x18" > /sys/kernel/debug/iommu/amd/iommu00/mmio
12 $ cat /sys/kernel/debug/iommu/amd/iommu00/mmio
18 What: /sys/kernel/debug/iommu/amd/iommu<x>/capability
23 capability register offset for iommu<x>, and the file outputs the
24 corresponding capability register value of iommu<x>.
28 $ echo "0x10" > /sys/kernel/debug/iommu/amd/iommu00/capability
29 $ cat /sys/kernel/debug/iommu/amd/iommu00/capability
[all …]
H A Ddebugfs-intel-iommu1 What: /sys/kernel/debug/iommu/intel/iommu_regset
5 This file dumps all the register contents for each IOMMU device.
11 $ sudo cat /sys/kernel/debug/iommu/intel/iommu_regset
13 IOMMU: dmar0 Register Base Address: 26be37000
24 IOMMU: dmar1 Register Base Address: fed90000
35 IOMMU: dmar2 Register Base Address: fed91000
46 What: /sys/kernel/debug/iommu/intel/ir_translation_struct
57 $ sudo cat /sys/kernel/debug/iommu/intel/ir_translation_struct
59 Remapped Interrupt supported on IOMMU: dmar0
66 Remapped Interrupt supported on IOMMU: dmar1
[all …]
/linux/arch/sparc/mm/
H A Diommu.c3 * iommu.c: IOMMU specific routines for memory management.
26 #include <asm/iommu.h>
60 struct iommu_struct *iommu; in sbus_iommu_init() local
67 iommu = kmalloc_obj(struct iommu_struct); in sbus_iommu_init()
68 if (!iommu) { in sbus_iommu_init()
69 prom_printf("Unable to allocate iommu structure\n"); in sbus_iommu_init()
73 iommu->regs = of_ioremap(&op->resource[0], 0, PAGE_SIZE * 3, in sbus_iommu_init()
75 if (!iommu->regs) { in sbus_iommu_init()
76 prom_printf("Cannot map IOMMU registers\n"); in sbus_iommu_init()
80 control = sbus_readl(&iommu->regs->control); in sbus_iommu_init()
[all …]

12345678910>>...28