| /freebsd/sys/contrib/device-tree/src/arm64/st/ |
| H A D | stm32mp251.dtsi | 33 interrupt-parent = <&intc>;
60 interrupt-parent = <&intc>;
116 intc: interrupt-controller@4ac00000 { label
148 interrupt-parent = <&intc>;
160 interrupt-parent = <&intc>;
540 interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
696 <&intc GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, /* EXTI_0 */
697 <&intc GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>,
698 <&intc GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>,
699 <&intc GIC_SPI 271 IRQ_TYPE_LEVEL_HIGH>,
[all …]
|
| /freebsd/sys/contrib/device-tree/Bindings/interrupt-controller/ |
| H A D | mrvl,intc.txt | 5 "mrvl,mmp-intc" on Marvel MMP,
6 "mrvl,mmp2-intc" along with "mrvl,mmp2-mux-intc" on MMP2 or
7 "marvell,mmp3-intc" with "mrvl,mmp2-mux-intc" on MMP3
9 If the interrupt controller is intc, address and length means the range
10 of the whole interrupt controller. The "marvell,mmp3-intc" controller
12 controller is mux-intc, address and length means one register. Since
13 address of mux-intc is in the range of intc. mux-intc is secondary
16 only required in mux-intc interrupt controller.
18 only required in mux-intc interrupt controller.
22 - mrvl,intc-nr-irqs : Specifies the number of interrupts in the interrupt
[all …]
|
| H A D | mrvl,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/mrvl,intc.yaml#
19 const: marvell,orion-intc
22 - mrvl,intc-nr-irqs
28 - mrvl,mmp-intc
29 - mrvl,mmp2-intc
39 - marvell,mmp3-intc
40 - mrvl,mmp2-mux-intc
49 const: mrvl,mmp2-mux-intc
70 - mrvl,mmp-intc
71 - mrvl,mmp2-intc
[all …]
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| H A D | ingenic,intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/ingenic,intc.yaml#
19 - ingenic,jz4740-intc
20 - ingenic,jz4760-intc
21 - ingenic,jz4780-intc
24 - ingenic,jz4775-intc
25 - ingenic,jz4770-intc
26 - ingenic,jz4760b-intc
27 - const: ingenic,jz4760-intc
29 - const: ingenic,x1000-intc
30 - const: ingenic,jz4780-intc
[all …]
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| H A D | amlogic,meson-gpio-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/amlogic,meson-gpio-intc.yaml#
26 - const: amlogic,meson-gpio-intc
29 - amlogic,meson8-gpio-intc
30 - amlogic,meson8b-gpio-intc
31 - amlogic,meson-gxbb-gpio-intc
32 - amlogic,meson-gxl-gpio-intc
33 - amlogic,meson-axg-gpio-intc
34 - amlogic,meson-g12a-gpio-intc
35 - amlogic,meson-sm1-gpio-intc
36 - amlogic,meson-a1-gpio-intc
[all …]
|
| H A D | renesas,irqc.yaml | 27 - renesas,intc-ex-r8a774a1 # RZ/G2M
28 - renesas,intc-ex-r8a774b1 # RZ/G2N
29 - renesas,intc-ex-r8a774c0 # RZ/G2E
30 - renesas,intc-ex-r8a774e1 # RZ/G2H
31 - renesas,intc-ex-r8a7795 # R-Car H3
32 - renesas,intc-ex-r8a7796 # R-Car M3-W
33 - renesas,intc-ex-r8a77961 # R-Car M3-W+
34 - renesas,intc-ex-r8a77965 # R-Car M3-N
35 - renesas,intc-ex-r8a77970 # R-Car V3M
36 - renesas,intc-ex-r8a77980 # R-Car V3H
[all …]
|
| H A D | csky,apb-intc.txt | 8 - csky,apb-intc is used in a lot of csky fpgas and socs, it support 64 irq nums.
9 - csky,dual-apb-intc consists of 2 apb-intc and 128 irq nums supported.
10 - csky,gx6605s-intc is gx6605s soc internal irq interrupt controller, 64 irq nums.
13 intc node bindings definition
23 Definition: must be "csky,apb-intc"
24 "csky,dual-apb-intc"
25 "csky,gx6605s-intc"
43 intc: interrupt-controller@500000 {
44 compatible = "csky,apb-intc";
50 intc: interrupt-controller@500000 {
[all …]
|
| H A D | amlogic,meson-gpio-intc.txt | 12 - compatible : must have "amlogic,meson8-gpio-intc" and either
13 "amlogic,meson8-gpio-intc" for meson8 SoCs (S802) or
14 "amlogic,meson8b-gpio-intc" for meson8b SoCs (S805) or
15 "amlogic,meson-gxbb-gpio-intc" for GXBB SoCs (S905) or
16 "amlogic,meson-gxl-gpio-intc" for GXL SoCs (S905X, S912)
17 "amlogic,meson-axg-gpio-intc" for AXG SoCs (A113D, A113X)
18 "amlogic,meson-g12a-gpio-intc" for G12A SoCs (S905D2, S905X2, S905Y2)
19 "amlogic,meson-sm1-gpio-intc" for SM1 SoCs (S905D3, S905X3, S905Y3)
20 "amlogic,meson-a1-gpio-intc" for A1 SoCs (A113L)
21 "amlogic,meson-s4-gpio-intc" for S4 SoCs (S802X2, S905Y4, S805X2G, S905W2)
[all …]
|
| H A D | ti,omap-intc-irq.txt | 1 Omap2/3 intc controller
3 On TI omap2 and 3 the intc interrupt controller can provide
8 "ti,omap2-intc"
9 "ti,omap3-intc"
10 "ti,dm814-intc"
11 "ti,dm816-intc"
12 "ti,am33xx-intc"
16 source, should be 1 for intc
23 intc: interrupt-controller@48200000 {
24 compatible = "ti,omap3-intc";
|
| H A D | brcm,l2-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/brcm,l2-intc.yaml#
20 - brcm,hif-spi-l2-intc
21 - brcm,upg-aux-aon-l2-intc
22 - const: brcm,l2-intc
25 - brcm,bcm2711-l2-intc
26 - const: brcm,l2-intc
28 - const: brcm,bcm7271-l2-intc
30 - const: brcm,l2-intc
66 compatible = "brcm,l2-intc";
70 interrupt-parent = <&intc>;
|
| H A D | renesas,intc-irqpin.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/renesas,intc-irqpin.yaml#
7 title: Renesas Interrupt Controller (INTC) for external pins
16 - renesas,intc-irqpin-r8a7740 # R-Mobile A1
17 - renesas,intc-irqpin-r8a7778 # R-Car M1A
18 - renesas,intc-irqpin-r8a7779 # R-Car H1
19 - renesas,intc-irqpin-sh73a0 # SH-Mobile AG5
20 - const: renesas,intc-irqpin
73 - renesas,intc-irqpin-r8a7740
74 - renesas,intc-irqpin-sh73a0
89 compatible = "renesas,intc-irqpin-r8a7740", "renesas,intc-irqpin";
|
| H A D | allwinner,sun6i-a31-r-intc.yaml | 4 $id: http://devicetree.org/schemas/interrupt-controller/allwinner,sun6i-a31-r-intc.yaml#
26 - const: allwinner,sun6i-a31-r-intc
29 - allwinner,sun8i-a83t-r-intc
30 - allwinner,sun8i-h3-r-intc
31 - allwinner,sun50i-a64-r-intc
32 - const: allwinner,sun6i-a31-r-intc
33 - const: allwinner,sun50i-h6-r-intc
59 compatible = "allwinner,sun50i-a64-r-intc",
60 "allwinner,sun6i-a31-r-intc";
|
| H A D | sifive,plic-1.0.0.txt | 39 to should be a riscv,cpu-intc node, which has a riscv node as parent.
51 &cpu0-intc 11
52 &cpu1-intc 11 &cpu1-intc 9
53 &cpu2-intc 11 &cpu2-intc 9
54 &cpu3-intc 11 &cpu3-intc 9
55 &cpu4-intc 11 &cpu4-intc 9>;
|
| H A D | qca,ath79-misc-intc.txt | 7 - compatible: has to be "qca,<soctype>-cpu-intc", "qca,ar7100-misc-intc" or
8 "qca,<soctype>-cpu-intc", "qca,ar7240-misc-intc"
24 compatible = "qca,ar9132-misc-intc", "qca,ar7100-misc-intc";
37 compatible = "qca,ar9331-misc-intc", qca,ar7240-misc-intc";
|
| /freebsd/sys/contrib/device-tree/src/arm/arm/ |
| H A D | arm-realview-pba8.dts | 45 interrupt-parent = <&intc>;
51 intc: interrupt-controller@1e000000 { label
62 interrupt-parent = <&intc>;
67 interrupt-parent = <&intc>;
80 interrupt-parent = <&intc>;
85 interrupt-parent = <&intc>;
90 interrupt-parent = <&intc>;
95 interrupt-parent = <&intc>;
100 interrupt-parent = <&intc>;
105 interrupt-parent = <&intc>;
[all …]
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| H A D | arm-realview-pbx-a9.dts | 89 interrupt-parent = <&intc>;
96 interrupt-parent = <&intc>;
102 interrupt-parent = <&intc>;
109 intc: interrupt-controller@1f000000 { label
120 interrupt-parent = <&intc>;
125 interrupt-parent = <&intc>;
130 interrupt-parent = <&intc>;
135 interrupt-parent = <&intc>;
140 interrupt-parent = <&intc>;
145 interrupt-parent = <&intc>;
[all …]
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| H A D | arm-realview-eb.dts | 51 intc: interrupt-controller@10040000 { label
68 interrupt-parent = <&intc>;
73 interrupt-parent = <&intc>;
78 interrupt-parent = <&intc>;
83 interrupt-parent = <&intc>;
89 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
99 interrupt-parent = <&intc>;
104 interrupt-parent = <&intc>;
109 interrupt-parent = <&intc>;
[all …]
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| H A D | arm-realview-eb-mp.dtsi | 41 intc: interrupt-controller@1f000100 { label
58 interrupt-parent = <&intc>;
65 interrupt-parent = <&intc>;
94 interrupt-parent = <&intc>;
101 interrupt-parent = <&intc>;
108 interrupt-parent = <&intc>;
123 interrupt-parent = <&intc>;
128 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
138 interrupt-parent = <&intc>;
[all …]
|
| /freebsd/sys/contrib/device-tree/src/mips/ingenic/ |
| H A D | jz4770.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4770-intc";
92 interrupt-parent = <&intc>;
133 interrupt-parent = <&intc>;
155 interrupt-parent = <&intc>;
170 interrupt-parent = <&intc>;
185 interrupt-parent = <&intc>;
200 interrupt-parent = <&intc>;
215 interrupt-parent = <&intc>;
230 interrupt-parent = <&intc>;
[all...] |
| H A D | jz4780.dtsi | 41 intc: interrupt-controller@10001000 { label
42 compatible = "ingenic,jz4780-intc";
113 interrupt-parent = <&intc>;
153 interrupt-parent = <&intc>;
180 interrupt-parent = <&intc>;
195 interrupt-parent = <&intc>;
210 interrupt-parent = <&intc>;
225 interrupt-parent = <&intc>;
240 interrupt-parent = <&intc>;
255 interrupt-parent = <&intc>;
[all …]
|
| H A D | x1000.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1000-intc", "ingenic,jz4780-intc";
121 interrupt-parent = <&intc>;
149 interrupt-parent = <&intc>;
173 interrupt-parent = <&intc>;
188 interrupt-parent = <&intc>;
203 interrupt-parent = <&intc>;
218 interrupt-parent = <&intc>;
227 interrupt-parent = <&intc>;
240 interrupt-parent = <&intc>;
[all …]
|
| H A D | x1830.dtsi | 32 intc: interrupt-controller@10001000 { label
33 compatible = "ingenic,x1830-intc", "ingenic,jz4780-intc";
114 interrupt-parent = <&intc>;
144 interrupt-parent = <&intc>;
168 interrupt-parent = <&intc>;
183 interrupt-parent = <&intc>;
198 interrupt-parent = <&intc>;
213 interrupt-parent = <&intc>;
222 interrupt-parent = <&intc>;
235 interrupt-parent = <&intc>;
[all …]
|
| H A D | jz4740.dtsi | 31 intc: interrupt-controller@10001000 { label
32 compatible = "ingenic,jz4740-intc";
81 interrupt-parent = <&intc>;
111 interrupt-parent = <&intc>;
136 interrupt-parent = <&intc>;
151 interrupt-parent = <&intc>;
166 interrupt-parent = <&intc>;
181 interrupt-parent = <&intc>;
192 interrupt-parent = <&intc>;
219 interrupt-parent = <&intc>;
[all …]
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| /freebsd/sys/contrib/device-tree/src/arc/ |
| H A D | axc003_idu.dtsi | 7 * Device tree for AXC003 CPU card: HS38x2 (Dual Core) with IDU intc
45 core_intc: archs-intc@cpu {
46 compatible = "snps,archs-intc";
52 compatible = "snps,archs-idu-intc";
60 * to uplink only 1 IRQ to ARC core intc
127 * This INTC is actually connected to DW APB GPIO
128 * which acts as a wire between MB INTC and CPU INTC.
129 * GPIO INTC is configured in platform init code
130 * and here we mimic direct connection from MB INTC to
131 * CPU INTC, thus we set "interrupts = <0 1>" instead of
[all …]
|
| H A D | axc001.dtsi | 37 core_intc: arc700-intc@cpu {
38 compatible = "snps,arc700-intc";
45 * to uplink only 1 IRQ to ARC core intc
83 * This INTC is actually connected to DW APB GPIO
84 * which acts as a wire between MB INTC and CPU INTC.
85 * GPIO INTC is configured in platform init code
86 * and here we mimic direct connection from MB INTC to
87 * CPU INTC, thus we set "interrupts = <7>" instead of
90 * This intc actually resides on MB, but we move it here to
92 * this intc to cpu intc are different for axs101 and axs103
|