IN0\-IN1 (full) in projects: linux - OpenGrok search results

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/linux/arch/mips/crypto/
H A D	poly1305-mips.pl	`2 # SPDX-License-Identifier: GPL-1.0+ OR BSD-3-Clause 5 # Written by Andy Polyakov, @dot-asm, originally for the OpenSSL 16 # R1x000 ~5.5/+130% (big-endian) 17 # Octeon II 2.50/+70% (little-endian) 21 # Add 32-bit code path. 25 # Modulo-scheduling reduction allows to omit dependency chain at the 30 # R1x000 ~9.8/? (big-endian) 31 # Octeon II 3.65/+140% (little-endian) 32 # MT7621/1004K 4.75/? (little-endian) 48 # - never ever touch $tp, "thread pointer", former $gp [o32 can be [all …]`
/linux/arch/arm64/crypto/
H A D	aes-neon.S	1 /* SPDX-License-Identifier: GPL-2.0-only / 3 linux/arch/arm64/crypto/aes-neon.S - AES cipher for ARMv8 NEON 5 * Copyright (C) 2013 - 2017 Linaro Ltd. <ard.biesheuvel@linaro.org> 22 /* special case for the neon-bs driver calling into this one for CTS */ 49 ld1 {v16.16b-v19.16b}, [\temp], #64 50 ld1 {v20.16b-v23.16b}, [\temp], #64 51 ld1 {v24.16b-v27.16b}, [\temp], #64 52 ld1 {v28.16b-v31.16b}, [\temp] 72 tbl \in\().16b, {v16.16b-v19.16b}, \in\().16b 74 tbx \in\().16b, {v20.16b-v23.16b}, v9.16b [all …]
H A D	aes-cipher-core.S	1 /* SPDX-License-Identifier: GPL-2.0-only / 20 .macro __pair1, sz, op, reg0, reg1, in0, in1e, in1d, shift 22 ubfiz \reg0, \in0, #2, #8 25 ubfx \reg0, \in0, #\shift, #8 31 32-bit quantities, i.e., 'ldrb w12, [tt, w12, uxtw #2]' is not a 49 .macro __pair0, sz, op, reg0, reg1, in0, in1e, in1d, shift 50 ubfx \reg0, \in0, #\shift, #8 56 .macro __hround, out0, out1, in0, in1, in2, in3, t0, t1, enc, sz, op 59 __pair\enc \sz, \op, w12, w13, \in0, \in1, \in3, 0 60 __pair\enc \sz, \op, w14, w15, \in1, \in2, \in0, 8 [all …]
H A D	sha512-ce-core.S	`1 /* SPDX-License-Identifier: GPL-2.0 / 3 sha512-ce-core.S - core SHA-384/SHA-512 transform using v8 Crypto Extensions 37 * The SHA-512 round constants 83 .macro dround, i0, i1, i2, i3, i4, rc0, rc1, in0, in1, in2, in3, in4 87 add v5.2d, v\rc0\().2d, v\in0\().2d 92 .ifnb \in1 94 sha512su0 v\in0\().2d, v\in1\().2d 97 .ifnb \in1 98 sha512su1 v\in0\().2d, v\in2\().2d, v5.2d 111 ld1 {v8.2d-v11.2d}, [x0] [all …]`
/linux/arch/powerpc/crypto/
H A D	aesp10-ppc.pl	2 # SPDX-License-Identifier: GPL-2.0 12 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org> 58 # The module is endian-agnostic in sense that it supports both big- 59 # and little-endian cases. Data alignment in parallelizable modes is 64 # is aligned programmatically, which in turn guarantees exception- 72 # Add XTS subroutine, 9x on little- and 12x improvement on big-endian 76 # Current large-block performance in cycles per byte processed with 77 # 128-bit key (less is better). 79 # CBC en-/decrypt CTR XTS 106 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or [all …]
H A D	aesp8-ppc.pl	2 # SPDX-License-Identifier: GPL-2.0 12 # Copyright (c) 2006-2017, CRYPTOGAMS by <appro@openssl.org> 58 # The module is endian-agnostic in sense that it supports both big- 59 # and little-endian cases. Data alignment in parallelizable modes is 64 # is aligned programmatically, which in turn guarantees exception- 72 # Add XTS subroutine, 9x on little- and 12x improvement on big-endian 76 # Current large-block performance in cycles per byte processed with 77 # 128-bit key (less is better). 79 # CBC en-/decrypt CTR XTS 106 ( $xlate="${dir}ppc-xlate.pl" and -f $xlate ) or [all …]
/linux/lib/
H A D	test_memcat_p.c	1 // SPDX-License-Identifier: GPL-2.0 17 /* Size of each of the NULL-terminated input arrays / 19 / Expected number of non-NULL elements in the output array / 20 #define EXPECT (INPUT_MAX 2 - 2) 24 struct test_struct in0, in1, out, p; in test_memcat_p_init() local 25 int err = -ENOMEM, i, r, total = 0; in test_memcat_p_init() 27 in0 = kcalloc(INPUT_MAX, sizeof(in0), GFP_KERNEL); in test_memcat_p_init() 28 if (!in0) in test_memcat_p_init() 31 in1 = kcalloc(INPUT_MAX, sizeof(in1), GFP_KERNEL); in test_memcat_p_init() 32 if (!in1) in test_memcat_p_init() [all …]
/linux/arch/arm/crypto/
H A D	aes-cipher-core.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 36 ldr\op \out, [ttab, \in, lsr #(8 \idx) - \sz] 42 .macro __hround, out0, out1, in0, in1, in2, in3, t3, t4, enc, sz, op, oldcpsr 43 __select \out0, \in0, 0 44 __select t0, \in1, 1 49 __select \out1, \in1, 0 53 __select t1, \in0, 1 65 __select \t4, \in0, 3 67 __select \t3, \in1, 2 76 * This is the final round and we're done with all data-dependent table [all …]`
H A D	ghash-ce-core.S	`1 /* SPDX-License-Identifier: GPL-2.0-only / 5 Copyright (C) 2015 - 2017 Linaro Ltd. 12 .arch armv8-a 13 .fpu crypto-neon-fp-armv8 20 IN1 .req q4 101 * This implementation of 64x64 -> 128 bit polynomial multiplication 102 * using vmull.p8 instructions (8x8 -> 16) is taken from the paper 105 * Ricardo Dahab (https://hal.inria.fr/hal-01506572) 107 * It has been slightly tweaked for in-order performance, and to allow 159 // PMULL (64x64->128) based reduction for CPUs that can do [all …]`
/linux/Documentation/devicetree/bindings/hwmon/
H A D	ti,adc128d818.yaml	1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 6 $schema: http://devicetree.org/meta-schemas/core.yaml# 11 - Javier Carrasco <javier.carrasco.cruz@gmail.com> 14 The ADC128D818 is a 12-Bit, 8-Channel Analog to Digital Converter (ADC) 31 Mode 0 - 7 single-ended voltage readings (IN0-IN6), 1 temperature 33 Mode 1 - 8 single-ended voltage readings (IN0-IN7), no temperature. 34 Mode 2 - 4 pseudo-differential voltage readings 35 (IN0-IN1, IN3-IN2, IN4-IN5, IN7-IN6), 1 temperature reading (internal). 36 Mode 3 - 4 single-ended voltage readings (IN0-IN3), 2 pseudo-differential [all …]
/linux/drivers/media/pci/ivtv/
H A D	ivtv-gpio.c	`1 // SPDX-License-Identifier: GPL-2.0-or-later 6 Copyright (C) 2005-2007 Hans Verkuil <hverkuil@xs4all.nl> 10 #include "ivtv-driver.h" 11 #include "ivtv-cards.h" 12 #include "ivtv-gpio.h" 15 #include <media/v4l2-ctrls.h> 21 * OUTPUT IN1 IN0 AM3 AM2 AM1 AM0 25 * IN1 IN0 54 * OUTPUT IN0 AM0 IN1 AM1 AM2 IN2 BR0 BR1 58 * IN0 IN1 IN2 [all …]`
/linux/Documentation/iio/
H A D	ad4695.rst	`1 .. SPDX-License-Identifier: GPL-2.0-only 26 ---------------- 30 4-wire mode 35 .. code-block:: 37 +-------------+ +-------------+ 38 \| CS \|<-+------\| CS \| 39 \| CNV \|<-+ \| \| 42 \| SDI \|<--------\| SDO \| 43 \| SDO \|-------->\| SDI \| 44 \| SCLK \|<--------\| SCLK \| [all …]`
/linux/Documentation/hwmon/
H A D	w83781d.rst	10 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports) 12 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83781d.pdf 18 Addresses scanned: I2C 0x28 - 0x2f, ISA 0x290 (8 I/O ports) 28 Datasheet: http://www.winbond-usa.com/products/winbond_products/pdfs/PCIC/w83783s.pdf 34 Addresses scanned: I2C 0x28 - 0x2f 42 - Frodo Looijaard <frodol@dds.nl>, 43 - Philip Edelbrock <phil@netroedge.com>, 44 - Mark Studebaker <mdsxyz123@yahoo.com> 47 ----------------- 67 ----------- [all …]
H A D	ltc4282.rst	1 .. SPDX-License-Identifier: GPL-2.0-only 12 Addresses scanned: - I2C 0x40 - 0x5A (7-bit) 13 Addresses scanned: - I2C 0x80 - 0xB4 with a step of 2 (8-bit) 17 https://www.analog.com/media/en/technical-documentation/data-sheets/ltc4282.pdf 25 from a live backplane. Using one or more external N-channel pass transistors, 31 parallel MOSFETs or support a 2-stage start-up that first charges the load 32 capacitance followed by enabling a low on-resistance path to the load. The 35 and power supplies must safely operate. Non-volatile configuration allows for 41 The following attributes are supported. Limits are read-write and all the other 42 attributes are read-only. Note that in0 and in1 are mutually exclusive. Enabling [all …]
H A D	dme1737.rst	18 Addresses scanned: none, address read from Super-I/O config space 34 Addresses scanned: none, address read from Super-I/O config space 43 ----------------- 52 Include non-standard LPC addresses 0x162e and 0x164e 55 - VIA EPIA SN18000 59 ----------- 63 and SCH5127 Super-I/O chips. These chips feature monitoring of 3 temp sensors 64 temp[1-3] (2 remote diodes and 1 internal), 8 voltages in[0-7] (7 external and 65 1 internal) and up to 6 fan speeds fan[1-6]. Additionally, the chips implement 66 up to 5 PWM outputs pwm[1-3,5-6] for controlling fan speeds both manually and [all …]
H A D	w83795.rst	`10 Addresses scanned: I2C 0x2c - 0x2f 18 Addresses scanned: I2C 0x2c - 0x2f 23 - Wei Song (Nuvoton) 24 - Jean Delvare <jdelvare@suse.de> 28 ----------- 35 - W83795G 40 13 VSEN1 (VCORE1) 10h in0 41 14 VSEN2 (VCORE2) 11h in1 94 - W83795ADG 99 10 VSEN1 (VCORE1) 10h in0 [all …]`
H A D	powr1220.rst	`19 ----------- 26 Voltages are sampled by a 12-bit ADC with a step size of 2 mV. 27 An in-line attenuator allows measurements from 0 to 6 V. The 37 in0 VMON1 38 in1 VMON2`
H A D	asb100.rst	`6 * Asus ASB100 and ASB100-A "Bach" 17 ----------- 19 This driver implements support for the Asus ASB100 and ASB100-A "Bach". 30 these, the ASB100-A also implements a single PWM controller for fans 2 and 48 - 0x0001 => in0 (?) 49 - 0x0002 => in1 (?) 50 - 0x0004 => in2 51 - 0x0008 => in3 52 - 0x0010 => temp1 [1]_ 53 - 0x0020 => temp2 [all …]`
H A D	gl518sm.rst	`21 - Frodo Looijaard <frodol@dds.nl>, 22 - Kyösti Mälkki <kmalkki@cc.hut.fi> 23 - Hong-Gunn Chew <hglinux@gunnet.org> 24 - Jean Delvare <jdelvare@suse.de> 27 ----------- 31 For the revision 0x00 chip, the in0, in1, and in2 values (+5V, +3V, 46 situation. Measurements are guaranteed between -10 degrees and +110 47 degrees, with a accuracy of +/-3 degrees. 77 you can easily miss once-only alarms.`
H A D	f71805f.rst	`44 ----------- 57 The Fintek F71806F/FG Super-I/O chip is essentially the same as the 65 ------------------ 67 Voltages are sampled by an 8-bit ADC with a LSB of 8 mV. The supported 69 need external resistors. An exception is in0, which is used to monitor 83 in0 VCC VCC3.3V int. int. 2.00 1.65 V 84 in1 VIN1 VTT1.2V 10K - 1.00 1.20 V 89 in6 VIN6 VCC1.5V 10K - 1.00 1.50 V 90 in7 VIN7 VCORE 10K - 1.00 ~1.40 V [1]_ 111 -------------- [all …]`
/linux/arch/sh/boards/mach-sdk7786/
H A D	gpio.c	`1 // SPDX-License-Identifier: GPL-2.0 19 "in0", "in1", "in2", "in3", "in4", "in5", "in6", "in7", 34 .label = "sdk7786-fpga", 38 .base = -1, /* don't care */`
/linux/drivers/acpi/riscv/
H A D	irq.c	1 // SPDX-License-Identifier: GPL-2.0-only 3 * Copyright (C) 2023-2024, Ventana Micro Systems Inc 31 static int irqchip_cmp_func(const void in0, const void in1) in irqchip_cmp_func() argument 33 struct acpi_probe_entry elem0 = (struct acpi_probe_entry )in0; in irqchip_cmp_func() 34 struct acpi_probe_entry elem1 = (struct acpi_probe_entry )in1; in irqchip_cmp_func() 36 return (elem0->type > elem1->type) - (elem0->type < elem1->type); in irqchip_cmp_func() 40 * On RISC-V, RINTC structures in MADT should be probed before any other 42 * controller subtypes in MADT of ACPI spec for RISC-V are defined in 43 * the incremental order like RINTC(24)->IMSIC(25)->APLIC(26)->PLIC(27). 51 if (nr == 1 \|\| !ACPI_COMPARE_NAMESEG(ACPI_SIG_MADT, ape->id)) in arch_sort_irqchip_probe() [all …]
/linux/Documentation/devicetree/bindings/iio/afe/
H A D	current-sense-shunt.yaml	`1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) 3 --- 4 $id: http://devicetree.org/schemas/iio/afe/current-sense-shunt.yaml# 5 $schema: http://devicetree.org/meta-schemas/core.yaml# 10 - Peter Rosin <peda@axentia.se> 13 When an io-channel measures the voltage over a current sense shunt, 20 const: current-sense-shunt 22 io-channels: 25 Channel node of a voltage io-channel. 27 "#io-channel-cells": [all …]`
/linux/drivers/i2c/busses/
H A D	i2c-icy.c	1 // SPDX-License-Identifier: GPL-2.0 3 * I2C driver for stand-alone PCF8584 style adapters on Zorro cards 8 * There has been a modern community re-print of this design in 2019: 17 * This started as a fork of i2c-elektor.c and has evolved since. 23 * As it turns out, i2c-algo-pcf is really written with i2c-elektor's 24 * edge-triggered ISA interrupts in mind, while the Amiga's Zorro bus has 25 * level-triggered interrupts. This means that once an interrupt occurs, we 29 * However, because of the PCF8584's host-side protocol, there is no good 32 * pin. This entails re-designing the core of i2c-algo-pcf in the future. 44 #include <linux/i2c-algo-pcf.h> [all …]
/linux/tools/testing/selftests/drivers/net/mlxsw/
H A D	qos_pfc.sh	2 # SPDX-License-Identifier: GPL-2.0 4 # This test injects a 10-MB burst of traffic with VLAN tag and 802.1p priority 8 # - the stream first ingresses through $swp1, where it is forwarded to $swp3 10 # - then it ingresses through $swp4. Here it is put to a lossless buffer and put 15 # - since $swp3 now can't send traffic, the traffic ingressing $swp1 is kept at 19 # - eventually the PFC pool gets some traffic out, headroom therefore gets some 24 # - if PFC works, all lossless flow packets that ingress through $swp1 should 28 # - it should all play out relatively quickly, so that SLL and HLL will not 31 # +-----------------------+ 37 # +---\|-------------------+ +--------------------+ [all …]

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