Searched full:imx7ulp_clk_spll_bus_clk (Results 1 – 3 of 3) sorted by relevance
57 #define IMX7ULP_CLK_SPLL_BUS_CLK 43 macro
105 <&scg1 IMX7ULP_CLK_SPLL_BUS_CLK>;
102 …hws[IMX7ULP_CLK_SPLL_BUS_CLK] = imx_clk_hw_divider_gate("spll_bus_clk", "spll_sel", CLK_SET_RATE_G… in imx7ulp_clk_scg1_init()