Searched full:imx7ulp_clk_sosc_bus_clk (Results 1 – 4 of 4) sorted by relevance
56 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
55 #define IMX7ULP_CLK_SOSC_BUS_CLK 41 macro
102 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
124 …hws[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_hw_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8… in imx7ulp_clk_scg1_init()