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/linux/arch/riscv/kvm/
H A Daia_imsic.c12 #include <linux/irqchip/riscv-imsic.h>
33 struct imsic { struct
44 * 1) Hardware: IMSIC VS-file (vsfile_cpu >= 0)
45 * 2) Software: IMSIC SW-file (vsfile_cpu < 0)
48 /* IMSIC VS-file */
55 /* IMSIC SW-file */
426 /* We can only read clear if we have a IMSIC VS-file */ in imsic_vsfile_read()
496 /* We can only access register if we have a IMSIC VS-file */ in imsic_vsfile_rw()
500 /* Check IMSIC register iselect */ in imsic_vsfile_rw()
524 /* We can only zero-out if we have a IMSIC VS-file */ in imsic_vsfile_local_clear()
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H A Daia.c13 #include <linux/irqchip/riscv-imsic.h>
623 * We release hgctrl->lock before notifying IMSIC in kvm_riscv_aia_disable()
628 /* Notify IMSIC */ in kvm_riscv_aia_disable()
666 * IMSIC guest files and number of bits in HGEIE in kvm_riscv_aia_init()
/linux/drivers/irqchip/
H A Dirq-riscv-imsic-platform.c7 #define pr_fmt(fmt) "riscv-imsic: " fmt
24 #include "irq-riscv-imsic-state.h"
32 global = &imsic->global; in imsic_cpu_page_phys()
62 local = per_cpu_ptr(imsic->global.local, vec->cpu); in imsic_irq_retrigger()
140 * state when changing target IMSIC vector from one CPU to another. in imsic_irq_set_affinity()
145 * 1) First write a temporary IMSIC vector to the device which in imsic_irq_set_affinity()
146 * has MSI address same as the old IMSIC vector but MSI data in imsic_irq_set_affinity()
147 * matches the new IMSIC vector. in imsic_irq_set_affinity()
149 * 2) Next write the new IMSIC vector to the device. in imsic_irq_set_affinity()
192 /* Do nothing if the old IMSIC vector does not belong to current CPU */ in imsic_irq_force_complete_move()
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H A Dirq-riscv-imsic-state.c7 #define pr_fmt(fmt) "riscv-imsic: " fmt
22 #include "irq-riscv-imsic-state.h"
59 struct imsic_priv *imsic; variable
63 return imsic ? &imsic->global : NULL; in imsic_get_global_config()
101 * IMSIC EIEx and EIPx registers. These registers in __imsic_eix_update()
112 * The IMSIC EIEx and EIPx registers are indirectly in __imsic_eix_update()
136 for_each_set_bit(i, lpriv->dirty_bitmap, imsic->global.nr_ids + 1) { in __imsic_local_sync()
186 tlocal = per_cpu_ptr(imsic->global.local, tvec->cpu); in __imsic_local_sync()
190 mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); in __imsic_local_sync()
195 mlocal = per_cpu_ptr(imsic->global.local, mvec->cpu); in __imsic_local_sync()
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H A Dirq-riscv-imsic-early.c7 #define pr_fmt(fmt) "riscv-imsic: " fmt
15 #include <linux/irqchip/riscv-imsic.h>
21 #include "irq-riscv-imsic-state.h"
28 struct imsic_local_config *local = per_cpu_ptr(imsic->global.local, cpu); in imsic_ipi_send()
49 /* Create IMSIC IPI multiplexing */ in imsic_ipi_domain_init()
57 /* Announce that IMSIC is providing IPIs */ in imsic_ipi_domain_init()
58 pr_info("%pfwP: providing IPIs using interrupt %d\n", imsic->fwnode, IMSIC_IPI_ID); in imsic_ipi_domain_init()
97 if (unlikely(!imsic->base_domain)) in imsic_handle_irq()
114 /* Mark per-CPU IMSIC state as online */ in imsic_starting_cpu()
140 /* Mark per-CPU IMSIC state as offline */ in imsic_dying_cpu()
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H A Dirq-riscv-aplic-msi.c13 #include <linux/irqchip/riscv-imsic.h>
197 * controller to be RISC-V AIA IMSIC controller. in aplic_msi_setup()
201 dev_err(dev, "IMSIC global config not found\n"); in aplic_msi_setup()
208 dev_err(dev, "IMSIC guest index bits big for APLIC LHXS\n"); in aplic_msi_setup()
215 dev_err(dev, "IMSIC hart index bits big for APLIC LHXW\n"); in aplic_msi_setup()
222 dev_err(dev, "IMSIC group index bits big for APLIC HHXW\n"); in aplic_msi_setup()
229 dev_err(dev, "IMSIC group index shift should be >= %d\n", in aplic_msi_setup()
235 dev_err(dev, "IMSIC group index shift big for APLIC HHXS\n"); in aplic_msi_setup()
258 * IMSIC and the IMSIC MSI domains are created later through in aplic_msi_setup()
H A DMakefile105 obj-$(CONFIG_RISCV_IMSIC) += irq-riscv-imsic-state.o irq-riscv-imsic-early.o irq-riscv-imsic-platf…
H A Dirq-riscv-intc.c98 * (such as PLIC, SBI IPI, CLINT, APLIC, IMSIC, etc) implement in riscv_intc_irq_eoi()
231 * interrupt controllers (such as PLIC, IMSIC and APLIC in riscv_intc_init()
H A Dirq-riscv-aplic-main.c10 #include <linux/irqchip/riscv-imsic.h>
/linux/arch/riscv/include/asm/
H A Dkvm_aia.h33 /* Number of group bits in IMSIC address */
36 /* Position of group bits in IMSIC address */
39 /* Number of hart bits in IMSIC address */
42 /* Number of guest bits in IMSIC address */
66 /* Guest physical address of IMSIC for this VCPU */
69 /* HART index of IMSIC extacted from guest physical address */
72 /* Internal state of IMSIC for this VCPU */
/linux/arch/riscv/include/uapi/asm/
H A Dkvm.h318 * 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
319 * 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
320 * 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
353 * value of the IMSIC register (range 0x70-0xFF) whereas the higher order
/linux/drivers/acpi/riscv/
H A Dirq.c41 * interrupt controller structures and IMSIC before APLIC. The interrupt
43 * the incremental order like RINTC(24)->IMSIC(25)->APLIC(26)->PLIC(27).
/linux/include/linux/irqchip/
H A Driscv-imsic.h72 /* Per-CPU IMSIC addresses */
/linux/arch/riscv/mm/
H A Dcacheflush.c35 * S-IMSIC, so the fence ensures previous data writes "happen before" in flush_icache_all()
/linux/include/acpi/
H A Dactbl2.h1559 u64 imsic_addr; /* IMSIC base address */
1560 u32 imsic_size; /* IMSIC size */
1571 /* 25: RISC-V IMSIC */
/linux/
H A DMAINTAINERS21318 F: drivers/irqchip/irq-riscv-imsic-*.c
21319 F: drivers/irqchip/irq-riscv-imsic-*.h
21322 F: include/linux/irqchip/riscv-imsic.h