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/linux/drivers/gpu/drm/amd/display/dc/resource/dcn401/
H A Ddcn401_resource.h34 #define HUBP_REG_LIST_DCN401_RI(id) \ argument
35 SRI_ARR(NOM_PARAMETERS_0, HUBPREQ, id), \
36 SRI_ARR(NOM_PARAMETERS_1, HUBPREQ, id), \
37 SRI_ARR(NOM_PARAMETERS_2, HUBPREQ, id), \
38 SRI_ARR(NOM_PARAMETERS_3, HUBPREQ, id), \
39 SRI_ARR(DCN_VM_MX_L1_TLB_CNTL, HUBPREQ, id), \
40 SRI_ARR(DCHUBP_CNTL, HUBP, id), \
41 SRI_ARR(HUBPREQ_DEBUG_DB, HUBP, id), \
42 SRI_ARR(HUBPREQ_DEBUG, HUBP, id), \
43 SRI_ARR(DCSURF_ADDR_CONFIG, HUBP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn32/
H A Ddcn32_resource.h210 #define ABM_DCN32_REG_LIST_RI(id) \ argument
211 SRI_ARR(DC_ABM1_HG_SAMPLE_RATE, ABM, id), \
212 SRI_ARR(DC_ABM1_LS_SAMPLE_RATE, ABM, id), \
213 SRI_ARR(BL1_PWM_BL_UPDATE_SAMPLE_RATE, ABM, id), \
214 SRI_ARR(DC_ABM1_HG_MISC_CTRL, ABM, id), \
215 SRI_ARR(DC_ABM1_IPCSC_COEFF_SEL, ABM, id), \
216 SRI_ARR(BL1_PWM_CURRENT_ABM_LEVEL, ABM, id), \
217 SRI_ARR(BL1_PWM_TARGET_ABM_LEVEL, ABM, id), \
218 SRI_ARR(BL1_PWM_USER_LEVEL, ABM, id), \
219 SRI_ARR(DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES, ABM, id), \
[all …]
/linux/drivers/staging/media/atomisp/pci/
H A Disp2401_input_system_private.h27 static inline hrt_data ibuf_ctrl_reg_load(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_load() argument
30 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_load()
31 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_load()
32 return ia_css_device_load_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in ibuf_ctrl_reg_load()
36 static inline void ibuf_ctrl_reg_store(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_reg_store() argument
40 assert(ID < N_IBUF_CTRL_ID); in ibuf_ctrl_reg_store()
41 assert(IBUF_CTRL_BASE[ID] != (hrt_address)-1); in ibuf_ctrl_reg_store()
43 ia_css_device_store_uint32(IBUF_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in ibuf_ctrl_reg_store()
47 static inline void ibuf_ctrl_get_proc_state(const ibuf_ctrl_ID_t ID, in ibuf_ctrl_get_proc_state() argument
57 ibuf_ctrl_reg_load(ID, reg_bank_offset + _IBUF_CNTRL_NUM_ITEMS_PER_STORE); in ibuf_ctrl_get_proc_state()
[all …]
/linux/Documentation/userspace-api/media/v4l/
H A Dbayer.svg3 …id="svg2" width="164.15mm" height="46.771mm" fill-rule="evenodd" stroke-linejoin="round" stroke-wi…
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H A Dnv12mt_example.svg17 id="svg2"
21 id="metadata953"><rdf:RDF><cc:Work
34 id="namedview951"
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49 id="defs9" /><defs
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51 id="defs107" /><defs
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H A Dnv12mt.svg17 id="svg2"
21 id="metadata383"><rdf:RDF><cc:Work
34 id="namedview381"
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49 id="presentation_clip_path"
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60 id="defs114" /><defs
[all …]
/linux/drivers/staging/media/atomisp/pci/hive_isp_css_common/host/
H A Dfifo_monitor.c44 const fifo_monitor_ID_t ID,
49 const fifo_monitor_ID_t ID,
54 const fifo_monitor_ID_t ID, in fifo_channel_get_state() argument
63 state->src_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
66 state->fifo_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
69 state->fifo_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
72 state->sink_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
77 state->src_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
80 state->fifo_accept = fifo_monitor_status_accept(ID, in fifo_channel_get_state()
83 state->fifo_valid = fifo_monitor_status_valid(ID, in fifo_channel_get_state()
[all …]
H A Dirq.c25 const irq_ID_t ID);
28 const irq_ID_t ID);
60 const irq_ID_t ID) in irq_clear_all() argument
64 assert(ID < N_IRQ_ID); in irq_clear_all()
65 assert(IRQ_N_CHANNEL[ID] <= HRT_DATA_WIDTH); in irq_clear_all()
67 if (IRQ_N_CHANNEL[ID] < HRT_DATA_WIDTH) { in irq_clear_all()
68 mask = ~((~(hrt_data)0) >> IRQ_N_CHANNEL[ID]); in irq_clear_all()
71 irq_reg_store(ID, in irq_clear_all()
80 const irq_ID_t ID, in irq_enable_channel() argument
83 unsigned int mask = irq_reg_load(ID, in irq_enable_channel()
[all …]
H A Dinput_formatter.c60 const input_formatter_ID_t ID) in input_formatter_rst() argument
65 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_rst()
67 addr = HIVE_IF_SRST_ADDRESS[ID]; in input_formatter_rst()
68 rst = HIVE_IF_SRST_MASK[ID]; in input_formatter_rst()
74 if (!HIVE_IF_BIN_COPY[ID]) { in input_formatter_rst()
75 input_formatter_reg_store(ID, addr, rst); in input_formatter_rst()
82 const input_formatter_ID_t ID) in input_formatter_get_alignment() argument
84 assert(ID < N_INPUT_FORMATTER_ID); in input_formatter_get_alignment()
86 return input_formatter_alignment[ID]; in input_formatter_get_alignment()
90 const input_formatter_ID_t ID, in input_formatter_set_fifo_blocking_mode() argument
[all …]
H A Dsp_private.h26 const sp_ID_t ID, in sp_ctrl_store() argument
30 assert(ID < N_SP_ID); in sp_ctrl_store()
31 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_store()
32 ia_css_device_store_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data), value); in sp_ctrl_store()
37 const sp_ID_t ID, in sp_ctrl_load() argument
40 assert(ID < N_SP_ID); in sp_ctrl_load()
41 assert(SP_CTRL_BASE[ID] != (hrt_address)-1); in sp_ctrl_load()
42 return ia_css_device_load_uint32(SP_CTRL_BASE[ID] + reg * sizeof(hrt_data)); in sp_ctrl_load()
46 const sp_ID_t ID, in sp_ctrl_getbit() argument
50 hrt_data val = sp_ctrl_load(ID, reg); in sp_ctrl_getbit()
[all …]
H A Dgp_device.c24 const gp_device_ID_t ID, in gp_device_get_state() argument
27 assert(ID < N_GP_DEVICE_ID); in gp_device_get_state()
30 state->syncgen_enable = gp_device_reg_load(ID, in gp_device_get_state()
32 state->syncgen_free_running = gp_device_reg_load(ID, in gp_device_get_state()
34 state->syncgen_pause = gp_device_reg_load(ID, in gp_device_get_state()
36 state->nr_frames = gp_device_reg_load(ID, in gp_device_get_state()
38 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
40 state->syngen_nr_pix = gp_device_reg_load(ID, in gp_device_get_state()
42 state->syngen_nr_lines = gp_device_reg_load(ID, in gp_device_get_state()
44 state->syngen_hblank_cycles = gp_device_reg_load(ID, in gp_device_get_state()
[all …]
/linux/drivers/staging/media/atomisp/pci/css_2401_system/host/
H A Dpixelgen_private.h33 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_load() argument
36 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_load()
37 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address) - 1); in pixelgen_ctrl_reg_load()
38 return ia_css_device_load_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof( in pixelgen_ctrl_reg_load()
47 const pixelgen_ID_t ID, in pixelgen_ctrl_reg_store() argument
51 assert(ID < N_PIXELGEN_ID); in pixelgen_ctrl_reg_store()
52 assert(PIXELGEN_CTRL_BASE[ID] != (hrt_address)-1); in pixelgen_ctrl_reg_store()
54 ia_css_device_store_uint32(PIXELGEN_CTRL_BASE[ID] + reg * sizeof(hrt_data), in pixelgen_ctrl_reg_store()
70 const pixelgen_ID_t ID, in pixelgen_ctrl_get_state() argument
74 pixelgen_ctrl_reg_load(ID, _PXG_COM_ENABLE_REG_IDX); in pixelgen_ctrl_get_state()
[all …]
H A Dcsi_rx_private.h38 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_load() argument
41 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_load()
42 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); in csi_rx_fe_ctrl_reg_load()
43 return ia_css_device_load_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof( in csi_rx_fe_ctrl_reg_load()
52 const csi_rx_frontend_ID_t ID, in csi_rx_fe_ctrl_reg_store() argument
56 assert(ID < N_CSI_RX_FRONTEND_ID); in csi_rx_fe_ctrl_reg_store()
57 assert(CSI_RX_FE_CTRL_BASE[ID] != (hrt_address)-1); in csi_rx_fe_ctrl_reg_store()
59 ia_css_device_store_uint32(CSI_RX_FE_CTRL_BASE[ID] + reg * sizeof(hrt_data), in csi_rx_fe_ctrl_reg_store()
68 const csi_rx_backend_ID_t ID, in csi_rx_be_ctrl_reg_load() argument
71 assert(ID < N_CSI_RX_BACKEND_ID); in csi_rx_be_ctrl_reg_load()
[all …]
/linux/drivers/i2c/busses/
H A Di2c-sh7760.c114 struct cami2c *id = ptr; in sh7760_i2c_irq() local
115 struct i2c_msg *msg = id->msg; in sh7760_i2c_irq()
119 msr = IN32(id, I2CMSR); in sh7760_i2c_irq()
120 fsr = IN32(id, I2CFSR); in sh7760_i2c_irq()
124 OUT32(id, I2CMCR, 0); in sh7760_i2c_irq()
125 OUT32(id, I2CSCR, 0); in sh7760_i2c_irq()
126 OUT32(id, I2CSAR, 0); in sh7760_i2c_irq()
127 id->status |= IDS_DONE | IDS_ARBLOST; in sh7760_i2c_irq()
139 OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST); in sh7760_i2c_irq()
140 OUT32(id, I2CMCR, MCR_MIE | MCR_FSB); in sh7760_i2c_irq()
[all …]
/linux/tools/testing/selftests/drivers/net/netdevsim/
H A Dnexthop.sh81 count=$($IP nexthop bucket show id $group_id nhid $nhid |
117 $IP nexthop add id 1 via 192.0.2.2 dev dummy1
118 nexthop_check "id 1" "id 1 via 192.0.2.2 dev dummy1 scope link trap"
124 $IP nexthop del id 1
137 $IP nexthop add id 1 via 192.0.2.2 dev dummy1
139 $IP nexthop add id 2 via 192.0.2.3 dev dummy1 &> /dev/null
155 $IP nexthop add id 1 via 192.0.2.2 dev dummy1
156 $IP nexthop add id 2 via 192.0.2.3 dev dummy1
158 $IP nexthop add id 10 group 1/2
159 nexthop_check "id 10" "id 10 group 1/2 trap"
[all …]
/linux/drivers/gpu/drm/amd/display/dc/resource/dcn35/
H A Ddcn35_resource.h49 #define OPP_REG_LIST_DCN20_RI(id) \ argument
50 OPP_REG_LIST_DCN10_RI(id), \
51 OPP_DPG_REG_LIST_RI(id), \
52 SRI_ARR(FMT_422_CONTROL, FMT, id), \
53 SRI_ARR(OPPBUF_CONTROL1, OPPBUF, id)
55 #define OPP_REG_LIST_DCN35_RI(id) \ argument
56 OPP_REG_LIST_DCN20_RI(id), \
57 SRI2_ARR(OPP_TOP_CLK_CONTROL, OPP, id)
59 #define VPG_DCN31_REG_LIST_RI(id) \ argument
60 SRI_ARR(VPG_GENERIC_STATUS, VPG, id), \
[all …]
/linux/Documentation/userspace-api/media/
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/linux/Documentation/userspace-api/media/dvb/
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/linux/drivers/gpu/drm/amd/display/dc/dpp/dcn30/
H A Ddcn30_dpp.h33 #define DPP_REG_LIST_DCN30_COMMON(id)\ argument
34 SRI(CM_DEALPHA, CM, id),\
35 SRI(CM_MEM_PWR_STATUS, CM, id),\
36 SRI(CM_BIAS_CR_R, CM, id),\
37 SRI(CM_BIAS_Y_G_CB_B, CM, id),\
38 SRI(PRE_DEGAM, CNVC_CFG, id),\
39 SRI(CM_GAMCOR_CONTROL, CM, id),\
40 SRI(CM_GAMCOR_LUT_CONTROL, CM, id),\
41 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
42 SRI(CM_GAMCOR_LUT_INDEX, CM, id),\
[all …]
/linux/tools/testing/selftests/net/
H A Dfib_nexthops.sh331 run_cmd "$IP nexthop add id $nhidstr via $ipstr$iter dev veth1"
332 check_nexthop "id $nhidstr" "id $nhidstr via $ipstr$iter dev veth1 scope link"
347 run_cmd "$IP nexthop add id $grpidstr group $grpstr"
348 check_nexthop "id $grpidstr" "id $grpidstr group $grpstr"
370 run_cmd "$IP nexthop add id 100 via $ipstr dev veth1"
371 run_cmd "$IP nexthop add id 1000 group 100 type resilient buckets $buckets"
456 run_cmd "$IP nexthop add id 61 via 2001:db8:91::2 fdb"
457 run_cmd "$IP nexthop add id 62 via 2001:db8:91::3 fdb"
458 run_cmd "$IP nexthop add id 102 group 61/62 fdb"
459 check_nexthop "id 102" "id 102 group 61/62 fdb"
[all …]
/linux/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_link_encoder.h39 #define AUX_REG_LIST(id)\ argument
40 SRI(AUX_CONTROL, DP_AUX, id), \
41 SRI(AUX_DPHY_RX_CONTROL0, DP_AUX, id), \
42 SRI(AUX_DPHY_RX_CONTROL1, DP_AUX, id)
44 #define HPD_REG_LIST(id)\ argument
45 SRI(DC_HPD_CONTROL, HPD, id)
47 #define LE_COMMON_REG_LIST_BASE(id) \ argument
52 SRI(DIG_BE_CNTL, DIG, id), \
53 SRI(DIG_BE_EN_CNTL, DIG, id), \
54 SRI(DP_CONFIG, DP, id), \
[all …]
/linux/drivers/gpu/drm/amd/display/dc/bios/
H A Dbios_parser_common.c63 enum object_enum_id id; in enum_id_from_bios_object_id() local
67 id = ENUM_ID_1; in enum_id_from_bios_object_id()
70 id = ENUM_ID_2; in enum_id_from_bios_object_id()
73 id = ENUM_ID_3; in enum_id_from_bios_object_id()
76 id = ENUM_ID_4; in enum_id_from_bios_object_id()
79 id = ENUM_ID_5; in enum_id_from_bios_object_id()
82 id = ENUM_ID_6; in enum_id_from_bios_object_id()
85 id = ENUM_ID_7; in enum_id_from_bios_object_id()
88 id = ENUM_ID_UNKNOWN; in enum_id_from_bios_object_id()
92 return id; in enum_id_from_bios_object_id()
[all …]
/linux/scripts/
H A Dextract_xc3028.pl163 # Firmware 0, type: BASE FW F8MHZ (0x00000003), id: (0000000000000000), size: 6635
167 write_le64(0x00000000, 0x00000000); # ID
172 # Firmware 1, type: BASE FW F8MHZ MTS (0x00000007), id: (0000000000000000), size: 6635
176 write_le64(0x00000000, 0x00000000); # ID
181 # Firmware 2, type: BASE FW FM (0x00000401), id: (0000000000000000), size: 6525
185 write_le64(0x00000000, 0x00000000); # ID
190 # Firmware 3, type: BASE FW FM INPUT1 (0x00000c01), id: (0000000000000000), size: 6539
194 write_le64(0x00000000, 0x00000000); # ID
199 # Firmware 4, type: BASE FW (0x00000001), id: (0000000000000000), size: 6633
203 write_le64(0x00000000, 0x00000000); # ID
[all …]
/linux/drivers/staging/media/atomisp/pci/hive_isp_css_include/host/
H A Dsp_public.h22 /*! Enable or disable the program complete irq signal of SP[ID]
24 \param ID[in] SP identifier
27 \return none, if(cnd) enable(SP[ID].irq) else disable(SP[ID].irq)
30 const sp_ID_t ID,
33 /*! Write to the status and control register of SP[ID]
35 \param ID[in] SP identifier
39 \return none, SP[ID].sc[reg] = value
42 const sp_ID_t ID,
46 /*! Read from the status and control register of SP[ID]
48 \param ID[in] SP identifier
[all …]
/linux/fs/bcachefs/
H A Dsnapshot.h34 static inline struct snapshot_t *__snapshot_t(struct snapshot_table *t, u32 id) in __snapshot_t() argument
36 u32 idx = U32_MAX - id; in __snapshot_t()
43 static inline const struct snapshot_t *snapshot_t(struct bch_fs *c, u32 id) in snapshot_t() argument
45 return __snapshot_t(rcu_dereference(c->snapshots), id); in snapshot_t()
48 static inline u32 bch2_snapshot_tree(struct bch_fs *c, u32 id) in bch2_snapshot_tree() argument
51 const struct snapshot_t *s = snapshot_t(c, id); in bch2_snapshot_tree()
52 id = s ? s->tree : 0; in bch2_snapshot_tree()
55 return id; in bch2_snapshot_tree()
58 static inline u32 __bch2_snapshot_parent_early(struct bch_fs *c, u32 id) in __bch2_snapshot_parent_early() argument
60 const struct snapshot_t *s = snapshot_t(c, id); in __bch2_snapshot_parent_early()
[all …]

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