xref: /linux/Documentation/devicetree/bindings/i2c/snps,designware-i2c.yaml (revision 9e4e86a604dfd06402933467578c4b79f5412b2c) 
1# SPDX-License-Identifier: GPL-2.0-only
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/i2c/snps,designware-i2c.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Synopsys DesignWare APB I2C Controller
8
9maintainers:
10  - Mika Westerberg <mika.westerberg@linux.intel.com>
11
12allOf:
13  - $ref: /schemas/i2c/i2c-controller.yaml#
14  - if:
15      properties:
16        compatible:
17          not:
18            contains:
19              const: mscc,ocelot-i2c
20    then:
21      properties:
22        reg:
23          maxItems: 1
24
25properties:
26  compatible:
27    oneOf:
28      - description: Generic Synopsys DesignWare I2C controller
29        const: snps,designware-i2c
30      - description: Renesas RZ/N1D I2C controller
31        items:
32          - const: renesas,r9a06g032-i2c  # RZ/N1D
33          - const: renesas,rzn1-i2c       # RZ/N1
34          - const: snps,designware-i2c
35      - description: Mobileye EyeQ DesignWare I2C controller
36        items:
37          - enum:
38              - mobileye,eyeq7h-i2c
39          - const: mobileye,eyeq6lplus-i2c
40          - const: snps,designware-i2c
41      - items:
42          - enum:
43              - mobileye,eyeq6lplus-i2c
44              - mscc,ocelot-i2c
45              - sophgo,sg2044-i2c
46              - thead,th1520-i2c
47          - const: snps,designware-i2c
48
49  reg:
50    minItems: 1
51    items:
52      - description: DW APB I2C controller memory mapped registers
53      - description: |
54          ICPU_CFG:TWI_DELAY registers to setup the SDA hold time.
55          This registers are specific to the Ocelot I2C-controller.
56
57  interrupts:
58    maxItems: 1
59
60  clocks:
61    minItems: 1
62    items:
63      - description: I2C controller reference clock source
64      - description: APB interface clock source
65
66  clock-names:
67    minItems: 1
68    items:
69      - const: ref
70      - const: pclk
71
72  resets:
73    maxItems: 1
74
75  clock-frequency:
76    description: Desired I2C bus clock frequency in Hz
77    enum: [100000, 400000, 1000000, 3400000]
78    default: 400000
79
80  i2c-sda-hold-time-ns:
81    description: |
82      The property should contain the SDA hold time in nanoseconds. This option
83      is only supported in hardware blocks version 1.11a or newer or on
84      Microsemi SoCs.
85
86  i2c-scl-falling-time-ns:
87    description: |
88      The property should contain the SCL falling time in nanoseconds.
89      This value is used to compute the tLOW period.
90    default: 300
91
92  i2c-sda-falling-time-ns:
93    description: |
94      The property should contain the SDA falling time in nanoseconds.
95      This value is used to compute the tHIGH period.
96    default: 300
97
98  dmas:
99    items:
100      - description: TX DMA Channel
101      - description: RX DMA Channel
102
103  dma-names:
104    items:
105      - const: tx
106      - const: rx
107
108  snps,bus-capacitance-pf:
109    $ref: /schemas/types.yaml#/definitions/uint32
110    description:
111      This property indicates the bus capacitance in picofarads (pF).
112      This value is used to compute the tHIGH and tLOW periods for high speed
113      mode.
114    enum: [100, 400]
115    default: 100
116
117  snps,clk-freq-optimized:
118    description:
119      This property indicates whether the hardware reduce its clock frequency
120      by reducing the internal latency required to generate the high period and
121      low period of SCL line.
122    type: boolean
123
124unevaluatedProperties: false
125
126required:
127  - compatible
128  - reg
129  - interrupts
130
131examples:
132  - |
133    i2c@f0000 {
134      compatible = "snps,designware-i2c";
135      reg = <0xf0000 0x1000>;
136      interrupts = <11>;
137      clock-frequency = <400000>;
138    };
139  - |
140    i2c@1120000 {
141      compatible = "snps,designware-i2c";
142      reg = <0x1120000 0x1000>;
143      interrupts = <12 1>;
144      clock-frequency = <400000>;
145      i2c-sda-hold-time-ns = <300>;
146      i2c-sda-falling-time-ns = <300>;
147      i2c-scl-falling-time-ns = <300>;
148      snps,bus-capacitance-pf = <400>;
149      snps,clk-freq-optimized;
150    };
151  - |
152    i2c@2000 {
153      compatible = "snps,designware-i2c";
154      reg = <0x2000 0x100>;
155      #address-cells = <1>;
156      #size-cells = <0>;
157      clock-frequency = <400000>;
158      clocks = <&i2cclk>;
159      interrupts = <0>;
160
161      eeprom@64 {
162        compatible = "atmel,24c02";
163        reg = <0x64>;
164      };
165    };
166  - |
167    i2c@100400 {
168      compatible = "mscc,ocelot-i2c", "snps,designware-i2c";
169      reg = <0x100400 0x100>, <0x198 0x8>;
170      pinctrl-0 = <&i2c_pins>;
171      pinctrl-names = "default";
172      interrupts = <8>;
173      clocks = <&ahb_clk>;
174    };
175...
176