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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dmscc,ocelot-icpu-intr.yaml4 $id: http://devicetree.org/schemas/interrupt-controller/mscc,ocelot-icpu-intr.yaml#
7 title: Microsemi Ocelot SoC ICPU Interrupt Controller
17 ICPU. It is connected directly to the MIPS core interrupt
24 - mscc,jaguar2-icpu-intr
25 - mscc,luton-icpu-intr
26 - mscc,ocelot-icpu-intr
27 - mscc,serval-icpu-intr
56 compatible = "mscc,ocelot-icpu-intr";
/linux/kernel/irq/
H A Dipi-mux.c31 struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu); in ipi_mux_mask() local
33 atomic_andnot(BIT(irqd_to_hwirq(d)), &icpu->enable); in ipi_mux_mask()
38 struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu); in ipi_mux_unmask() local
41 atomic_or(ibit, &icpu->enable); in ipi_mux_unmask()
50 if (atomic_read(&icpu->bits) & ibit) in ipi_mux_unmask()
56 struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu); in ipi_mux_send_mask() local
62 icpu = per_cpu_ptr(ipi_mux_pcpu, cpu); in ipi_mux_send_mask()
71 pending = atomic_fetch_or_release(ibit, &icpu->bits); in ipi_mux_send_mask()
86 if (!(pending & ibit) && (atomic_read(&icpu->enable) & ibit)) in ipi_mux_send_mask()
122 struct ipi_mux_cpu *icpu = this_cpu_ptr(ipi_mux_pcpu); in ipi_mux_process() local
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/linux/drivers/irqchip/
H A Dirq-mscc-ocelot.c142 "icpu", handle_level_irq, in vcoreiii_irq_init()
199 IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
207 IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init);
215 IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
223 IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init);
/linux/drivers/base/
H A Dcacheinfo.c998 unsigned int icpu; in update_per_cpu_data_slice_size() local
1000 for_each_cpu(icpu, cpu_map) { in update_per_cpu_data_slice_size()
1001 if (!cpu_online && icpu == cpu) in update_per_cpu_data_slice_size()
1003 update_per_cpu_data_slice_size_cpu(icpu); in update_per_cpu_data_slice_size()
1004 setup_pcp_cacheinfo(icpu); in update_per_cpu_data_slice_size()
/linux/arch/mips/boot/dts/mscc/
H A Dluton.dtsi60 compatible = "mscc,luton-icpu-intr";
H A Dserval.dtsi63 compatible = "mscc,serval-icpu-intr";
H A Djaguar2.dtsi64 compatible = "mscc,jaguar2-icpu-intr";
H A Docelot.dtsi60 compatible = "mscc,ocelot-icpu-intr";
/linux/drivers/net/dsa/
H A Dvitesse-vsc73xx-core.c570 dev_err(vsc->dev, "unable to read iCPU control\n"); in vsc73xx_detect()
574 /* The iCPU can always be used but can boot in different ways. in vsc73xx_detect()
584 "iCPU enabled boots from SI, has external memory\n"); in vsc73xx_detect()
590 "iCPU enabled boots from PI/SI, no external memory\n"); in vsc73xx_detect()
595 "iCPU enabled, boots from PI external memory\n"); in vsc73xx_detect()
600 dev_info(vsc->dev, "iCPU disabled, no external memory\n"); in vsc73xx_detect()