| /freebsd/sys/contrib/device-tree/include/dt-bindings/pinctrl/ |
| H A D | k210-fpioa.h | 1 /* SPDX-License-Identifier: GPL-2.0+ */
11 * kendryte-standalone-sdk/lib/drivers/include/fpioa.h
32 #define K210_PCF_UARTHS_RX 18 /* UART High speed Receiver */
33 #define K210_PCF_UARTHS_TX 19 /* UART High speed Transmitter */
38 #define K210_PCF_GPIOHS0 24 /* GPIO High speed 0 */
39 #define K210_PCF_GPIOHS1 25 /* GPIO High speed 1 */
40 #define K210_PCF_GPIOHS2 26 /* GPIO High speed 2 */
41 #define K210_PCF_GPIOHS3 27 /* GPIO High speed 3 */
42 #define K210_PCF_GPIOHS4 28 /* GPIO High speed 4 */
43 #define K210_PCF_GPIOHS5 29 /* GPIO High speed 5 */
[all …]
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| /freebsd/sys/dev/sound/isa/ |
| H A D | sb.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
66 #define DSP_CMD_DAC8 0x14 /* single cycle 8-bit dma out */
67 #define DSP_CMD_ADC8 0x24 /* single cycle 8-bit dma in */
70 #define DSP_CMD_DAC8_AUTO 0x1c /* auto 8-bit dma out */
71 #define DSP_CMD_ADC8_AUTO 0x2c /* auto 8-bit dma out */
73 #define DSP_CMD_HSSIZE 0x48 /* high speed dma count */
74 #define DSP_CMD_HSDAC_AUTO 0x90 /* high speed dac, auto */
75 #define DSP_CMD_HSADC_AUTO 0x98 /* high speed adc, auto */
82 #define DSP_CMD_DAC2 0x16 /* 2-bit adpcm dma out (cont) */
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| /freebsd/sys/contrib/device-tree/Bindings/phy/ |
| H A D | qcom,usb-snps-femto-v2.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,usb-snps-femto-v2.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Synopsys Femto High-Speed USB PHY V2
10 - Wesley Cheng <quic_wcheng@quicinc.com>
13 Qualcomm High-Speed USB PHY
18 - items:
19 - enum:
20 - qcom,sa8775p-usb-hs-phy
[all …]
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| H A D | qcom,snps-eusb2-repeater.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/qcom,snps-eusb2-repeater.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Abel Vesa <abel.vesa@linaro.org>
19 - items:
20 - enum:
21 - qcom,pm7550ba-eusb2-repeater
22 - const: qcom,pm8550b-eusb2-repeater
23 - enum:
[all …]
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| H A D | socionext,uniphier-usb3hs-phy.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Socionext UniPhier USB3 High-Speed (HS) PHY
12 Although the controller includes High-Speed PHY and Super-Speed PHY,
13 this describes about High-Speed PHY.
16 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
21 - socionext,uniphier-pro5-usb3-hsphy
22 - socionext,uniphier-pxs2-usb3-hsphy
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| H A D | microchip,sparx5-serdes.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/phy/microchip,sparx5-serdes.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Steen Hegelund <steen.hegelund@microchip.com>
21 * Rx built-in fault detector (loss-of-lock/loss-of-signal)
22 * Adjustable tx de-emphasis (FFE)
31 The SERDES6G is a high-speed SERDES interface, which can operate at
34 * 100 Mbps (100BASE-FX)
35 * 1.25 Gbps (SGMII/1000BASE-X/1000BASE-KX)
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| /freebsd/sys/contrib/device-tree/Bindings/usb/ |
| H A D | usb.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Greg Kroah-Hartman <gregkh@linuxfoundation.org>
22 phy-names:
26 usb-phy:
27 $ref: /schemas/types.yaml#/definitions/phandle-array
38 UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is selected, UTMI+ low
40 serial is specified and High-Speed Inter-Chip feature if HSIC is
46 maximum-speed:
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| H A D | samsung-hsotg.txt | 1 Samsung High Speed USB OTG controller
2 -----------------------------
5 It gives functionality of OTG-compliant USB 2.0 host and device with
6 support for USB 2.0 high-speed (480Mbps) and full-speed (12 Mbps)
12 -----
15 - compatible: "samsung,s3c6400-hsotg" should be used for all currently
17 - interrupts: specifier of interrupt signal of interrupt controller,
19 - clocks: contains an array of clock specifiers:
20 - first entry: OTG clock
21 - clock-names: contains array of clock names:
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| /freebsd/usr.bin/morse/ |
| H A D | morse.6 | 39 .Op Fl w Ar speed
40 .Op Fl c Ar speed
50 .Bl -tag -width indent
66 .It Fl w Ar speed
67 Set the sending speed in words per minute.
69 speed of 20 WPM is used.
70 .It Fl c Ar speed
73 This is independent of the speed
156 characters with the high-order bit set
159 .Bl -tag -width ".Li ISO8859-15" -compact
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| /freebsd/sys/contrib/device-tree/Bindings/mmc/ |
| H A D | mmc-controller.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/mmc/mmc-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Ulf Hansson <ulf.hansson@linaro.org>
25 "#address-cell
[all...] |
| H A D | cdns,sdhci.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Masahiro Yamada <yamada.masahiro@socionext.com>
15 - enum:
16 - amd,pensando-elba-sd4hc
17 - microchip,mpfs-sd4hc
18 - socionext,uniphier-sd4hc
19 - const: cdns,sd4hc
39 cdns,phy-input-delay-sd-highspeed:
[all …]
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| H A D | sdhci-am654.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
4 ---
5 $id: http://devicetree.org/schemas/mmc/sdhci-am654.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
11 - Ulf Hansson <ulf.hansson@linaro.org>
14 - $ref: sdhci-common.yaml#
19 - enum:
20 - ti,am62-sdhci
21 - ti,am64-sdhci-4bit
[all …]
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| H A D | sdhci-sprd.txt | 1 * Spreadtrum SDHCI controller (sdhci-sprd)
7 and the properties used by the sdhci-sprd driver.
10 - compatible: Should contain "sprd,sdhci-r11".
11 - reg: physical base address of the controller and length.
12 - interrupts: Interrupts used by the SDHCI controller.
13 - clocks: Should contain phandle for the clock feeding the SDHCI controller
14 - clock-names: Should contain the following:
15 "sdio" - SDIO source clock (required)
16 "enable" - gate clock which used for enabling/disabling the device (required)
17 "2x_enable" - gate clock controlling the device for some special platforms (optional)
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/i2c/ |
| H A D | i2c-exynos5.txt | 1 * Samsung's High Speed I2C controller
3 The Samsung's High Speed I2C controller is used to interface with I2C devices
7 - compatible: value should be.
8 -> "samsung,exynos5-hsi2c", (DEPRECATED)
11 -> "samsung,exynos5250-hsi2c", for i2c compatible with HSI2C available
13 -> "samsung,exynos5260-hsi2c", for i2c compatible with HSI2C available
15 -> "samsung,exynos7-hsi2c", for i2c compatible with HSI2C available
18 - reg: physical base address of the controller and length of memory mapped
20 - interrupts: interrupt number to the cpu.
21 - #address-cells: always 1 (for i2c addresses)
[all …]
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| H A D | i2c-exynos5.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/i2c/i2c-exynos5.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Samsung's High Speed I2C controller
10 - Krzysztof Kozlowski <krzk@kernel.org>
13 The Samsung's High Speed I2C controller is used to interface with I2C devices
19 Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml for details.
24 - enum:
25 - samsung,exynos5250-hsi2c # Exynos5250 and Exynos5420
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| /freebsd/sys/contrib/zstd/ |
| H A D | CHANGELOG | 2 perf: Regain Minimal memset()-ing During Reuse of Compression Contexts (@Cyan4973, #2969)
7 perf: rebalanced compression levels, to better match the intended speed/level curve, by @senhuang42
9 perf: slightly faster high speed modes (strategies fast & dfast), by @felixhandte
12 perf: faster mid-level compression speed in presence of highly repetitive patterns, by @senhuang42
13 perf: minor compression ratio improvements for small data at high levels, by @cyan4973
15 perf: faster compression speed on incompressible data, by @bindhvo
16 perf: on-demand reduced ZSTD_DCtx state size, using build macro ZSTD_DECODER_INTERNAL_BUFFER, at a …
20 build: improved meson unofficial build, by @eli-schwartz
22 …t advanced parameters information when compressing in very verbose mode (``-vv`), by @Svetlitski-FB
25 api: Various functions promoted from experimental to stable API: (#2579-2581, @senhuang42)
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/powerpc/4xx/ |
| H A D | hsta.txt | 2 ppc476gtr High Speed Serial Assist (HSTA) node
5 The 476gtr SoC contains a high speed serial assist module attached
6 between the plb4 and plb6 system buses to provide high speed data
14 - compatible : "ibm,476gtr-hsta-msi", "ibm,hsta-msi"
15 - reg : register mapping for the HSTA MSI space
16 - interrupts : ordered interrupt mapping for each MSI in the register
|
| /freebsd/sys/contrib/device-tree/src/arm/st/ |
| H A D | stih410-b2260.dts | 1 // SPDX-License-Identifier: GPL-2.0-only
6 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 compatible = "st,stih410-b2260", "st,stih410";
15 stdout-path = &uart1;
29 compatible = "gpio-leds";
30 led-user-green-1 {
33 linux,default-trigger = "heartbeat";
34 default-state = "off";
37 led-user-green-2 {
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm/intel/socfpga/ |
| H A D | socfpga_cyclone5_chameleon96.dts | 1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 #include <dt-bindings/gpio/gpio.h>
14 compatible = "novtech,chameleon96", "altr,socfpga-cyclone5", "altr,socfpga";
18 stdout-path = "serial0:115200n8";
28 compatible = "regulator-fixed";
29 regulator-name = "3.3V";
30 regulator-min-microvolt = <3300000>;
31 regulator-max-microvolt = <3300000>;
35 compatible = "gpio-leds";
40 linux,default-trigger = "heartbeat";
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/clock/ |
| H A D | google,gs101-clock.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/clock/google,gs101-clock.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Peter Griffin <peter.griffin@linaro.org>
16 is OSCCLK (24.576 MHz). That external clock must be defined as a fixed-rate
19 CMU_TOP is a top-level CMU, where all base clocks are prepared using PLLs and
25 'dt-bindings/clock/gs101.h' header.
30 - google,gs101-cmu-top
31 - google,gs101-cmu-apm
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| /freebsd/sys/contrib/device-tree/Bindings/ |
| H A D | xilinx.txt | 10 Each IP-core has a set of parameters which the FPGA designer can use to
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
33 (generic-name): an open firmware-style name that describes the
36 (ip-core-name): the name of the ip block (given after the BEGIN
38 and all underscores '_' converted to dashes '-'.
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| /freebsd/usr.bin/mkuzip/ |
| H A D | mkuzip.8 | 1 .\"-
2 .\" Copyright (c) 2004-2016 Maxim Sobolev <sobomax@FreeBSD.org>
48 class will be able to decompress the resulting image at run-time.
56 .Bl -enum
69 .Bl -tag -width indent
79 It has vastly slower compression speed and moderately slower decompression
80 speed.
85 It also has faster compression and decompression speed than zlib.
86 In the very high compression
88 settings, it does not offer quite as high a compression ratio as
[all …]
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | nvidia,tegra-pinmux-common.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/pinctrl/nvidia,tegra-pinmux-common.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jonathan Hunter <jonathanh@nvidia.com>
14 Please refer to pinctrl-bindings.txt in this directory for details of the
22 pin configuration parameters, such as pull-up, tristate, drive strength,
46 $ref: /schemas/types.yaml#/definitions/string-array
57 description: Pull-down/up setting to apply to the pin.
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| /freebsd/sys/dev/ow/ |
| H A D | owll_if.m | 1 #-
33 # Dallas Semiconductor 1-Wire bus Link Layer (owll)
36 # 1-Wire protocol specification.
39 # Note: 1-Wire is a registered trademark of Maxim Integrated Products, Inc.
43 # SoCs have a 1-Wire controller with more smarts or hardware offload.
45 # as well as both usb and i2c 1-Wire controllers.
50 # Two speed classes are defined: Regular speed and Overdrive speed.
74 # Note: This is the polling / busy-wait interface. An interrupt-based interface
75 # may be different. But an interrupt-based, non-blocking interface can be tricky.
80 # WRITE-ONE (see above for timings) From Figure 4-1 AN-937
[all …]
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| /freebsd/sys/contrib/device-tree/src/arm64/mediatek/ |
| H A D | mt2712-evb.dts | 5 * SPDX-License-Identifier: (GPL-2.0 OR MIT)
8 /dts-v1/;
9 #include <dt-bindings/gpio/gpio.h>
14 chassis-type = "embedded";
15 compatible = "mediatek,mt2712-evb", "mediatek,mt2712";
27 stdout-path = "serial0:921600n8";
30 cpus_fixed_vproc0: regulator-vproc-buck0 {
31 compatible = "regulator-fixed";
32 regulator-name = "vproc_buck0";
33 regulator-min-microvolt = <1000000>;
[all …]
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