| /linux/arch/powerpc/platforms/85xx/ |
| H A D | sgy_cts1000.c | 10 #define pr_fmt(fmt) "gpio-halt: " fmt
29 .compatible = "sgy,gpio-halt",
48 panic("Halt failed\n"); in gpio_halt_cb()
69 NULL, 0, GPIOD_OUT_LOW, "gpio-halt"); in __gpio_halt_probe()
72 dev_err(&pdev->dev, "failed to request halt GPIO: %d\n", err); in __gpio_halt_probe()
80 "gpio-halt", pdev); in __gpio_halt_probe()
89 /* Register our halt function */ in __gpio_halt_probe()
90 ppc_md.halt = gpio_halt_cb; in __gpio_halt_probe()
93 dev_info(&pdev->dev, "registered halt GPIO, irq: %d\n", halt_irq); in __gpio_halt_probe()
122 ppc_md.halt = NULL; in gpio_halt_remove()
[all …]
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| /linux/Documentation/virt/kvm/ |
| H A D | halt-polling.rst | 4 The KVM halt polling system
7 The KVM halt polling system provides a feature within KVM whereby the latency
19 invoked. Thus halt polling is especially useful on workloads with very short
20 wakeup periods where the time spent halt polling is minimised and the time
23 The generic halt polling code is implemented in:
31 Halt Polling Interval
35 as the halt polling interval, is increased and decreased based on the perceived
47 During polling if a wakeup source is received within the halt polling interval,
75 the time between when the halt polling function is
98 | | halt polling interval is | |
[all …]
|
| /linux/Documentation/devicetree/bindings/remoteproc/ |
| H A D | qcom,sc7280-adsp-pil.yaml | 76 qcom,halt-regs:
80 four offsets within syscon for q6, modem, nc and qv6 halt registers.
84 - description: offset to the Q6 halt register
85 - description: offset to the modem halt register
86 - description: offset to the nc halt register
87 - description: offset to the vq6 halt register
132 - qcom,halt-regs
176 qcom,halt-regs = <&tcsr_mutex 0x23000 0x25000 0x28000 0x33000>;
|
| /linux/arch/alpha/kernel/ |
| H A D | head.S | 88 # It is handy, on occasion, to make halt actually just loop.
94 .globl halt
95 .ent halt
96 halt: label
99 .end halt
|
| /linux/Documentation/devicetree/bindings/bus/ |
| H A D | qcom,ssc-block-bus.yaml | 82 qcom,halt-regs:
84 description: describes how to locate the ssc AXI halt register
88 - description: offset for the ssc AXI halt register
103 - qcom,halt-regs
142 qcom,halt-regs = <&tcsr_mutex_regs 0x26000>;
|
| /linux/drivers/clk/qcom/ |
| H A D | clk-branch.h | 17 * @halt_reg: halt register
19 * @halt_check: type of halt checking to perform
31 #define BRANCH_HALT 0 /* pol: 1 = halt */
33 #define BRANCH_HALT_ENABLE 1 /* pol: 0 = halt */
36 #define BRANCH_HALT_SKIP 3 /* Don't check halt bit */
|
| /linux/Documentation/devicetree/bindings/watchdog/ |
| H A D | atmel,sama5d4-wdt.yaml | 46 atmel,idle-halt:
56 atmel,dbg-halt:
77 atmel,dbg-halt;
78 atmel,idle-halt;
|
| H A D | atmel,at91sam9-wdt.yaml | 71 atmel,idle-halt:
82 atmel,dbg-halt:
123 atmel,dbg-halt;
124 atmel,idle-halt;
|
| /linux/drivers/net/usb/ |
| H A D | rndis_host.c | 303 struct rndis_halt *halt; in generic_rndis_bind() member
445 memset(u.halt, 0, sizeof *u.halt); in generic_rndis_bind()
446 u.halt->msg_type = cpu_to_le32(RNDIS_MSG_HALT); in generic_rndis_bind()
447 u.halt->msg_len = cpu_to_le32(sizeof *u.halt); in generic_rndis_bind()
448 (void) rndis_command(dev, (void *)u.halt, CONTROL_BUFFER_SIZE); in generic_rndis_bind()
476 struct rndis_halt *halt; in rndis_unbind() local
479 halt = kzalloc(CONTROL_BUFFER_SIZE, GFP_KERNEL); in rndis_unbind()
480 if (halt) { in rndis_unbind()
481 halt->msg_type = cpu_to_le32(RNDIS_MSG_HALT); in rndis_unbind()
482 halt->msg_len = cpu_to_le32(sizeof *halt); in rndis_unbind()
[all …]
|
| /linux/tools/usb/ |
| H A D | hcd-tests.sh | 9 # - halt: needs bulk sink+src, tests halt set/clear from host
20 #TYPES='control out in halt'
233 halt)
236 # firmware can halt them from the device, don't worry much if
239 echo "test 13: $COUNT halt set/clear"
|
| /linux/arch/arm/mach-lpc32xx/ |
| H A D | pm.c | 15 * direct-run, and halt modes. When switching between halt and run modes,
17 * mode is not used in normal operation. Halt mode is used when the
31 * Halt mode:
55 * Enter halt mode - CPU and buses will stop
|
| /linux/arch/alpha/boot/ |
| H A D | head.S | 98 .globl halt
99 .ent halt
100 halt: label
103 .end halt
|
| /linux/Documentation/translations/zh_CN/virt/ |
| H A D | guest-halt-polling.rst | 3 :Original: Documentation/virt/guest-halt-polling.rst
13 .. _cn_virt_guest-halt-polling:
16 客户机停机轮询机制（Guest halt polling）
|
| /linux/tools/perf/pmu-events/arch/x86/silvermont/ |
| H A D | pipeline.json | 164 …halt state. The core enters the halt state when it is running the HLT instruction. This event is a…
173 …unts the number of core cycles while the core is not in a halt state. The core enters the halt sta…
181 … the number of reference cycles that the core is not in a halt state. The core enters the halt sta…
189 …halt state. The core enters the halt state when it is running the HLT instruction. This event is a…
|
| /linux/arch/mips/include/asm/dec/ |
| H A D | kn02ba.h | 17 #define KN02BA_CPU_INR_HALT 6 /* HALT button */
40 #define KN02BA_IO_INR_PBNC 1 /* ~HALT button debouncer */
41 #define KN02BA_IO_INR_PBNO 0 /* HALT button debouncer */
|
| H A D | kn03.h | 26 #define KN03_CPU_INR_HALT 6 /* HALT button */
49 #define KN03_IO_INR_PBNC 1 /* ~HALT button debouncer */
50 #define KN03_IO_INR_PBNO 0 /* HALT button debouncer */
|
| /linux/drivers/staging/media/ipu3/ |
| H A D | ipu3-mmu.c | 94 * imgu_mmu_set_halt - set CIO gate halt bit
96 * @halt: Desired state of the gate bit.
101 static void imgu_mmu_set_halt(struct imgu_mmu *mmu, bool halt) in imgu_mmu_set_halt() argument
106 writel(halt, mmu->base + REG_GP_HALT); in imgu_mmu_set_halt()
108 val, (val & 1) == halt, 1000, 100000); in imgu_mmu_set_halt()
111 dev_err(mmu->dev, "failed to %s CIO gate halt\n", in imgu_mmu_set_halt()
112 halt ? "set" : "clear"); in imgu_mmu_set_halt()
|
| /linux/tools/perf/pmu-events/arch/x86/alderlaken/ |
| H A D | pipeline.json | 300 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
309 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
325 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
334 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
342 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt stat
[all...] |
| /linux/tools/perf/pmu-events/arch/x86/elkhartlake/ |
| H A D | pipeline.json | 162 …unts the number of core cycles while the core is not in a halt state. The core enters the halt sta…
171 …unts the number of core cycles while the core is not in a halt state. The core enters the halt sta…
179 … the number of reference cycles that the core is not in a halt state. The core enters the halt sta…
187 … the number of reference cycles that the core is not in a halt state. The core enters the halt sta…
196 … the number of reference cycles that the core is not in a halt state. The core enters the halt sta…
|
| /linux/tools/perf/pmu-events/arch/x86/snowridgex/ |
| H A D | pipeline.json | 162 …unts the number of core cycles while the core is not in a halt state. The core enters the halt sta…
171 …unts the number of core cycles while the core is not in a halt state. The core enters the halt sta…
179 … the number of reference cycles that the core is not in a halt state. The core enters the halt sta…
187 … the number of reference cycles that the core is not in a halt state. The core enters the halt sta…
196 … the number of reference cycles that the core is not in a halt state. The core enters the halt sta…
|
| /linux/tools/perf/pmu-events/arch/x86/alderlake/ |
| H A D | pipeline.json | 597 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses fixed counter 1.",
607 "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. The core frequency may change from time to time. For this reason this event may have a changing ratio with regards to time. This event uses a programmable general purpose performance counter.",
675 "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses fixed counter 2.",
681 "BriefDescription": "Reference cycles when the core is not in halt state.",
684 "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt stat
[all...] |
| /linux/drivers/spi/ |
| H A D | spi-slave-system-control.c | 5 * halt, and suspend.
18 * # halt='\x38\x76'
20 * # spidev_test -D /dev/spidev2.0 -p $suspend # or $reboot, $poweroff, $halt
|
| /linux/drivers/cpuidle/governors/ |
| H A D | haltpoll.c | 39 /* allow shrinking guest halt poll */
63 /* Halt if no event occurred on poll window */ in haltpoll_select()
73 /* Last state was halt: poll */ in haltpoll_select()
|
| /linux/drivers/usb/dwc2/ |
| H A D | hcd_intr.c | 399 * holds the reason for the halt.
766 * interrupt for the appropriate queue is enabled so that the halt request can
793 dev_vdbg(hsotg->dev, "Halt on queue\n"); in dwc2_halt_channel()
810 * halt to be queued when the periodic schedule is in dwc2_halt_channel()
853 * Always halt and release the host channel to make it available for in dwc2_complete_non_periodic_xfer()
865 * halt the channel. (In DMA mode, this call simply releases in dwc2_complete_non_periodic_xfer()
1258 * Halt the channel so the transfer can be re-started from in dwc2_hc_nak_intr()
1338 * Halt the channel so the transfer can be re-started in dwc2_hc_ack_intr()
1473 * Halt the channel and re-start the transfer so the PING protocol in dwc2_hc_nyet_intr()
1611 * Force a channel halt. Don't call dwc2_halt_channel because that won't in dwc2_hc_ahberr_intr()
[all …]
|
| /linux/tools/perf/pmu-events/arch/x86/skylake/ |
| H A D | pipeline.json | 215 "BriefDescription": "Reference cycles when the core is not in halt state.",
218 …halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT ins…
250 "BriefDescription": "Core cycles when the thread is not in halt state",
253 …halt state. The thread enters the halt state when it is running the HLT instruction. This event is…
259 …iefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
266 "BriefDescription": "Thread cycles when thread is not in halt state",
270 …the number of thread cycles while the thread is not in a halt state. The thread enters the halt st…
275 …iefDescription": "Core cycles when at least one thread on the physical core is not in halt state.",
|