Home
last modified time | relevance | path

Searched full:hfpll (Results 1 – 10 of 10) sorted by relevance

/linux/Documentation/devicetree/bindings/clock/
H A Dqcom,hfpll.yaml4 $id: http://devicetree.org/schemas/clock/qcom,hfpll.yaml#
13 The HFPLL is used as CPU PLL on various Qualcomm SoCs.
19 - qcom,msm8974-hfpll
20 - qcom,msm8976-hfpll-a53
21 - qcom,msm8976-hfpll-a72
22 - qcom,msm8976-hfpll-cci
23 - qcom,qcs404-hfpll
24 - const: qcom,hfpll
29 - description: HFPLL registers
63 compatible = "qcom,msm8974-hfpll";
H A Dqcom,krait-cc.txt20 Definition: reference to the clock parents of hfpll, secondary muxes.
/linux/drivers/clk/qcom/
H A Dhfpll.c15 #include "clk-hfpll.h"
87 { .compatible = "qcom,msm8976-hfpll-a53", .data = &msm8976_a53 },
88 { .compatible = "qcom,msm8976-hfpll-a72", .data = &msm8976_a72 },
89 { .compatible = "qcom,msm8976-hfpll-cci", .data = &msm8976_cci },
90 { .compatible = "qcom,qcs404-hfpll", .data = &qcs404 },
92 { .compatible = "qcom,hfpll", .data = &qcs404 },
160 .name = "qcom-hfpll",
166 MODULE_DESCRIPTION("QCOM HFPLL Clock Driver");
168 MODULE_ALIAS("platform:qcom-hfpll");
H A Dclk-hfpll.c13 #include "clk-hfpll.h"
19 /* Initialize a HFPLL at a given rate and enable it. */
94 /* Enable an already-configured HFPLL. */
222 WARN(1, "HFPLL %s is ON, but not locked!\n", in clk_hfpll_init()
H A Dkrait-cc.c41 * while the hfpll is getting reprogrammed.
106 init.name = kasprintf(GFP_KERNEL, "hfpll%s_div", s); in krait_add_div()
111 parent_name = kasprintf(GFP_KERNEL, "hfpll%s", s); in krait_add_div()
259 hfpll_name = kasprintf(GFP_KERNEL, "hfpll%s", s); in krait_add_pri_mux()
406 * two different rates to force a HFPLL reinit under all in krait_cc_probe()
H A DMakefile16 clk-qcom-y += clk-hfpll.o
167 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
H A DKconfig1321 tristate "High-Frequency PLL (HFPLL) Clock Controller"
H A Dgcc-ipq806x.c25 #include "clk-hfpll.h"
H A Dgcc-msm8960.c26 #include "clk-hfpll.h"
/linux/arch/arm64/boot/dts/qcom/
H A Dqcs404.dtsi1327 compatible = "qcom,qcs404-hfpll";