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/linux/drivers/gpu/drm/amd/display/modules/hdcp/
H A Dhdcp_log.h29 #define HDCP_LOG_ERR(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__) argument
30 #define HDCP_LOG_VER(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__) argument
31 #define HDCP_LOG_FSM(hdcp, ...) DRM_DEBUG_KMS(__VA_ARGS__) argument
32 #define HDCP_LOG_TOP(hdcp, ...) pr_debug("[HDCP_TOP]:"__VA_ARGS__) argument
33 #define HDCP_LOG_DDC(hdcp, ...) pr_debug("[HDCP_DDC]:"__VA_ARGS__) argument
36 #define HDCP_ERROR_TRACE(hdcp, status) \ argument
37 HDCP_LOG_ERR(hdcp, \
39 hdcp->config.index, \
41 mod_hdcp_state_id_to_str(hdcp->state.id), \
42 hdcp->state.stay_count)
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H A Dhdcp1_execution.c26 #include "hdcp.h"
28 static inline enum mod_hdcp_status validate_bksv(struct mod_hdcp *hdcp) in validate_bksv() argument
34 memcpy(bksv, hdcp->auth.msg.hdcp1.bksv, sizeof(hdcp->auth.msg.hdcp1.bksv)); in validate_bksv()
45 static inline enum mod_hdcp_status check_ksv_ready(struct mod_hdcp *hdcp) in check_ksv_ready() argument
47 if (is_dp_hdcp(hdcp)) in check_ksv_ready()
48 return (hdcp->auth.msg.hdcp1.bstatus & DP_BSTATUS_READY) ? in check_ksv_ready()
51 return (hdcp->auth.msg.hdcp1.bcaps & DRM_HDCP_DDC_BCAPS_KSV_FIFO_READY) ? in check_ksv_ready()
56 static inline enum mod_hdcp_status check_hdcp_capable_dp(struct mod_hdcp *hdcp) in check_hdcp_capable_dp() argument
58 return (hdcp->auth.msg.hdcp1.bcaps & DP_BCAPS_HDCP_CAPABLE) ? in check_hdcp_capable_dp()
63 static inline enum mod_hdcp_status check_r0p_available_dp(struct mod_hdcp *hdcp) in check_r0p_available_dp() argument
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H A Dhdcp_log.c27 #include "hdcp.h"
54 void mod_hdcp_log_ddc_trace(struct mod_hdcp *hdcp) in mod_hdcp_log_ddc_trace() argument
56 if (is_hdcp1(hdcp)) { in mod_hdcp_log_ddc_trace()
57 HDCP_DDC_READ_TRACE(hdcp, "BKSV", hdcp->auth.msg.hdcp1.bksv, in mod_hdcp_log_ddc_trace()
58 sizeof(hdcp->auth.msg.hdcp1.bksv)); in mod_hdcp_log_ddc_trace()
59 HDCP_DDC_READ_TRACE(hdcp, "BCAPS", &hdcp->auth.msg.hdcp1.bcaps, in mod_hdcp_log_ddc_trace()
60 sizeof(hdcp->auth.msg.hdcp1.bcaps)); in mod_hdcp_log_ddc_trace()
61 HDCP_DDC_READ_TRACE(hdcp, "BSTATUS", in mod_hdcp_log_ddc_trace()
62 (uint8_t *)&hdcp->auth.msg.hdcp1.bstatus, in mod_hdcp_log_ddc_trace()
63 sizeof(hdcp->auth.msg.hdcp1.bstatus)); in mod_hdcp_log_ddc_trace()
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H A Dhdcp_psp.c29 #include "hdcp.h"
34 static void hdcp2_message_init(struct mod_hdcp *hdcp, in hdcp2_message_init() argument
37 in->session_handle = hdcp->auth.id; in hdcp2_message_init()
49 struct mod_hdcp *hdcp, uint8_t index) in remove_display_from_topology_v2() argument
51 struct psp_context *psp = hdcp->config.psp.handle; in remove_display_from_topology_v2()
54 get_active_display_at_index(hdcp, index); in remove_display_from_topology_v2()
77 HDCP_TOP_REMOVE_DISPLAY_TRACE(hdcp, display->index); in remove_display_from_topology_v2()
85 struct mod_hdcp *hdcp, uint8_t index) in remove_display_from_topology_v3() argument
87 struct psp_context *psp = hdcp->config.psp.handle; in remove_display_from_topology_v3()
90 get_active_display_at_index(hdcp, index); in remove_display_from_topology_v3()
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H A Dhdcp1_transition.c26 #include "hdcp.h"
28 enum mod_hdcp_status mod_hdcp_hdcp1_transition(struct mod_hdcp *hdcp, in mod_hdcp_hdcp1_transition() argument
34 struct mod_hdcp_connection *conn = &hdcp->connection; in mod_hdcp_hdcp1_transition()
35 struct mod_hdcp_link_adjustment *adjust = &hdcp->connection.link.adjust; in mod_hdcp_hdcp1_transition()
37 switch (current_state(hdcp)) { in mod_hdcp_hdcp1_transition()
42 increment_stay_counter(hdcp); in mod_hdcp_hdcp1_transition()
46 set_state_id(hdcp, output, H1_A1_EXCHANGE_KSVS); in mod_hdcp_hdcp1_transition()
64 set_state_id(hdcp, output, in mod_hdcp_hdcp1_transition()
87 set_watchdog_in_ms(hdcp, 5000, output); in mod_hdcp_hdcp1_transition()
88 set_state_id(hdcp, output, H1_A8_WAIT_FOR_READY); in mod_hdcp_hdcp1_transition()
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H A DMakefile23 # Makefile for the 'hdcp' sub-module of DAL.
26 HDCP = hdcp_ddc.o hdcp_log.o hdcp_psp.o hdcp.o \ macro
30 AMD_DAL_HDCP = $(addprefix $(AMDDALPATH)/modules/hdcp/,$(HDCP))
H A Dhdcp_psp.h77 /* for all security interfaces which reference displays such as HDCP */
108 /* for all security interfaces which reference displays such as HDCP */
109 …/* link_hdcp_cap means link is HDCP-capable for audio HDCP capable property(informational), not fo…
232 /* HDCP related enumerations */
324 /* input/output structures for HDCP commands */
482 /* Common input structure for HDCP callbacks */
501 /* Common output structure for HDCP callbacks */
/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-mhdp8546-hdcp.c16 #include "cdns-mhdp8546-hdcp.h"
165 dev_dbg(mhdp->dev, "HDCP Error = %d", err); in cdns_mhdp_hdcp_handle_status()
339 dev_dbg(mhdp->dev, "HDCP: Start 2.2 Authentication\n"); in cdns_mhdp_hdcp_auth_22()
363 dev_dbg(mhdp->dev, "HDCP: Starting 1.4 Authentication\n"); in cdns_mhdp_hdcp_auth_14()
396 dev_dbg(mhdp->dev, "[%s:%d] HDCP is being disabled...\n", in _cdns_mhdp_hdcp_disable()
427 dev_err(mhdp->dev, "HDCP authentication failed (%d tries/%d)\n", in _cdns_mhdp_hdcp_enable()
438 mutex_lock(&mhdp->hdcp.mutex); in cdns_mhdp_hdcp_check_link()
439 if (mhdp->hdcp.value == DRM_MODE_CONTENT_PROTECTION_UNDESIRED) in cdns_mhdp_hdcp_check_link()
447 "[%s:%d] HDCP link failed, retrying authentication\n", in cdns_mhdp_hdcp_check_link()
452 mhdp->hdcp.value = DRM_MODE_CONTENT_PROTECTION_DESIRED; in cdns_mhdp_hdcp_check_link()
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H A Dcdns-mhdp8546-hdcp.h24 #define HDCP_CONFIG_1_4 BIT(0) /* use HDCP 1.4 only */
25 #define HDCP_CONFIG_2_2 BIT(1) /* use HDCP 2.2 only */
26 /* use All HDCP versions */
/linux/include/drm/intel/
H A Di915_hdcp_interface.h17 * enum hdcp_port_type - HDCP port implementation type defined by ME/GSC FW
18 * @HDCP_PORT_TYPE_INVALID: Invalid hdcp port type
33 * enum hdcp_wired_protocol - HDCP adaptation used on the port
34 * @HDCP_PROTOCOL_INVALID: Invalid HDCP adaptation protocol
35 * @HDCP_PROTOCOL_HDMI: HDMI adaptation of HDCP used on the port
36 * @HDCP_PROTOCOL_DP: DP adaptation of HDCP used on the port
79 * struct hdcp_port_data - intel specific HDCP port data
82 * @port_type: HDCP port type as per ME/GSC FW classification
83 * @protocol: HDCP adaptation as per ME/GSC FW
119 * @close_hdcp_session: Close the Wired HDCP Tx session per port.
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/linux/drivers/gpu/drm/msm/hdmi/
H A Dhdmi_hdcp.c21 /* QFPROM Registers for HDMI/HDCP */
217 DBG("hdcp irq %x", hdcp_int_status); in msm_hdmi_hdcp_irq()
296 * Indicates that the last HDCP HW DDC transfer failed. in msm_reset_hdcp_ddc_failures()
297 * This occurs when a transfer is attempted with HDCP DDC in msm_reset_hdcp_ddc_failures()
316 pr_info("%s: Unable to clear HDCP DDC Failure\n", in msm_reset_hdcp_ddc_failures()
319 /* Re-Enable HDCP DDC */ in msm_reset_hdcp_ddc_failures()
404 DBG("HDCP REAUTH WORK"); in msm_hdmi_hdcp_reauth_work()
407 * This is needed to reset the HDCP cipher engine so that when we in msm_hdmi_hdcp_reauth_work()
416 /* Disable HDCP interrupts */ in msm_hdmi_hdcp_reauth_work()
429 /* Disable encryption and disable the HDCP block */ in msm_hdmi_hdcp_reauth_work()
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danalogix-i2c-dptx.h15 /* HDCP Status Register */
20 /* HDCP Control Register 0 */
29 /* HDCP Function Enabled */
32 /* HDCP Receiver BSTATUS Register 0 */
34 /* HDCP Receiver BSTATUS Register 1 */
37 /* HDCP Embedded "Blue Screen" Content Registers */
42 /* HDCP Wait R0 Timing Register */
45 /* HDCP Link Integrity Check Timer Register */
48 /* HDCP Repeater Ready Wait Timer Register */
51 /* HDCP Auto Timer Register */
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/linux/drivers/gpu/drm/display/
H A Ddrm_hdcp_helper.c261 * @drm_dev: drm_device for which HDCP revocation check is requested
262 * @ksvs: List of KSVs (HDCP receiver IDs)
265 * This function reads the HDCP System renewability Message(SRM Table)
266 * from userspace as a firmware and parses it for the revoked HDCP
275 * 1. Renewability chapter on 55th page of HDCP 1.4 specification
276 …* https://www.digital-cp.com/sites/default/files/specifications/HDCP%20Specification%20Rev1_4_Secu…
277 * 2. Renewability chapter on 63rd page of HDCP 2.2 specification
278 …* https://www.digital-cp.com/sites/default/files/specifications/HDCP%20on%20HDMI%20Specification%2…
319 { DRM_MODE_HDCP_CONTENT_TYPE0, "HDCP Type0" },
320 { DRM_MODE_HDCP_CONTENT_TYPE1, "HDCP Type1" },
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/linux/Documentation/devicetree/bindings/display/
H A Dallwinner,sun8i-a83t-dw-hdmi.yaml54 - description: HDCP Clock
55 - description: HDCP Bus Clock
64 - const: hdcp
65 - const: hdcp-bus
71 - description: HDCP Reset
77 - const: hdcp
227 clock-names = "iahb", "isfr", "tmds", "cec", "hdcp",
228 "hdcp-bus";
230 reset-names = "ctrl", "hdcp";
/linux/Documentation/driver-api/mei/
H A Dhdcp.rst3 HDCP:
11 according the HDCP 2.2 spec. The Intel graphics sends the created blob
19 the HDCP encryption keys to Intel graphics hardware.
24 .. kernel-doc:: drivers/misc/mei/hdcp/mei_hdcp.c
30 .. kernel-doc:: drivers/misc/mei/hdcp/mei_hdcp.c
/linux/include/drm/display/
H A Ddrm_hdcp.h14 /* Period of hdcp checks (to ensure we're still authenticated) */
29 /* Slave address for the HDCP registers in the receiver */
35 /* HDCP register offsets for HDMI/DVI devices */
54 * - Type0: Can be transmitted with HDCP 1.4+
55 * - Type1: Can be transmitted with HDCP 2.2+
139 * The TxCaps field specified in the HDCP HDMI, DP specs
146 /* Reserved for HDCP and DP Spec. Read as Zero */
257 * Helper functions to convert 24bit big endian hdcp sequence number to
/linux/drivers/misc/mei/hdcp/
H A Dmei_hdcp.c5 * mei_hdcp.c: HDCP client driver for mei bus
14 * The mei_hdcp driver acts as a translation layer between HDCP 2.2
34 * @data: Intel HW specific hdcp data
97 * @data: Intel HW specific hdcp data
177 * @data: Intel HW specific hdcp data
234 * @data: Intel HW specific hdcp data
293 * @data: Intel HW specific hdcp data
349 * @data: Intel HW specific hdcp data
408 * @data: Intel HW specific hdcp data
467 * @data: Intel HW specific hdcp data
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/linux/drivers/media/i2c/
H A Dtda1997x_regs.h241 #define HDMI_FLAGS_HDCP BIT(4) /* HDCP detected */
299 /* HDCP DE Control */
314 /* HDCP EP Filter Control */
437 #define INTERRUPT_HDCP BIT(6) /* HDCP module */
446 #define MASK_HDCP_MTP BIT(7) /* HDCP MTP busy */
447 #define MASK_HDCP_DLMTP BIT(4) /* HDCP end download MTP to SRAM */
448 #define MASK_HDCP_DLRAM BIT(3) /* HDCP end download keys from SRAM */
449 #define MASK_HDCP_ENC BIT(2) /* HDCP ENC */
450 #define MASK_STATE_C5 BIT(1) /* HDCP State C5 reached */
478 #define MASK_HDCP_DDC_SW BIT(2) /* HDCP DDC switching finished */
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dite,it6505.yaml17 fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications.
28 Each IT6505 chip comes preprogrammed with an unique HDCP key,
29 in compliance with the HDCP 1.3 standard so as to provide secure
31 purchase any HDCP keys or ROMs.
/linux/Documentation/devicetree/bindings/soc/imx/
H A Dfsl,imx8mp-hdmi-blk-ctrl.yaml43 - const: hdcp
65 - const: hdcp
97 "hdcp", "hrv";
/linux/drivers/gpu/drm/amd/display/dc/hdcp/
H A DMakefile21 # Makefile for the 'hdcp' sub-component of DAL.
26 AMD_DAL_HDCP_MSG = $(addprefix $(AMDDALPATH)/dc/hdcp/,$(HDCP_MSG))
/linux/drivers/gpu/drm/amd/display/include/
H A Dhdcp_msg_types.h32 /* HDCP 1.4 */
52 /* HDCP 2.2 */
/linux/drivers/gpu/drm/bridge/
H A Dsil-sii8620.h863 /* HDCP Polling Control and Status, default value: 0x70 */
873 /* HDCP Interrupt 0, default value: 0x00 */
876 /* HDCP Interrupt 0 Mask, default value: 0x00 */
879 /* HDCP General Control 0, default value: 0x02 */
890 /* HDCP General Control 1, default value: 0x08 */
898 /* HDCP Misc Control, default value: 0x00 */
906 /* HDCP RPT SMNG K, default value: 0x00 */
909 /* HDCP RPT SMNG In, default value: 0x00 */
912 /* HDCP Auth Status, default value: 0x00 */
915 /* HDCP RPT RCVID Out, default value: 0x00 */
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/linux/Documentation/userspace-api/media/v4l/
H A Dext-ctrls-dv.rst23 Identification Data, :ref:`vesaedid`) and HDCP (High-bandwidth Digital
24 Content Protection System, :ref:`hdcp`) processing, allowing the
25 device to do the fairly slow EDID/HDCP handling in advance. This allows
/linux/Documentation/admin-guide/perf/
H A Dmeson-ddr-pmu.rst30 + hdcp - from HDCP controller

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