xref: /linux/Documentation/devicetree/bindings/dpll/microchip,zl30731.yaml (revision 91ec2035134982b98fab0609a9fd8480e8217dc1) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/dpll/microchip,zl30731.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Microchip Azurite DPLL device
8
9maintainers:
10  - Ivan Vecera <ivecera@redhat.com>
11
12description:
13  Microchip Azurite DPLL (ZL3073x) is a family of DPLL devices that
14  provides up to 5 independent DPLL channels, up to 10 differential or
15  single-ended inputs and 10 differential or 20 single-ended outputs.
16  These devices support both I2C and SPI interfaces.
17  The ZL3064x line card timing ICs  share the ZL3073x register map
18  and are described with a fallback to the register equivalent ZL3073x
19  part.
20
21properties:
22  compatible:
23    oneOf:
24      - enum:
25          - microchip,zl30731
26          - microchip,zl30732
27          - microchip,zl30733
28          - microchip,zl30734
29          - microchip,zl30735
30      - items:
31          - const: microchip,zl30643
32          - const: microchip,zl30733
33
34  reg:
35    maxItems: 1
36
37required:
38  - compatible
39  - reg
40
41allOf:
42  - $ref: /schemas/dpll/dpll-device.yaml#
43  - $ref: /schemas/spi/spi-peripheral-props.yaml#
44
45unevaluatedProperties: false
46
47examples:
48  - |
49    i2c {
50      #address-cells = <1>;
51      #size-cells = <0>;
52
53      dpll@70 {
54        compatible = "microchip,zl30732";
55        reg = <0x70>;
56        dpll-types = "pps", "eec";
57
58        input-pins {
59          #address-cells = <1>;
60          #size-cells = <0>;
61
62          sync0: pin@0 { /* REF0P - 1 PPS sync source */
63            reg = <0>;
64            connection-type = "ext";
65            label = "SMA1";
66            supported-frequencies-hz = /bits/ 64 <1>;
67          };
68
69          pin@1 { /* REF0N - clock source, can pair with sync0 */
70            reg = <1>;
71            connection-type = "ext";
72            label = "SMA2";
73            supported-frequencies-hz = /bits/ 64 <10000 10000000>;
74            ref-sync-sources = <&sync0>;
75          };
76        };
77
78        output-pins {
79          #address-cells = <1>;
80          #size-cells = <0>;
81
82          pin@3 { /* OUT1N */
83            reg = <3>;
84            connection-type = "gnss";
85            esync-control;
86            label = "Output 1";
87            supported-frequencies-hz = /bits/ 64 <1 10000>;
88          };
89        };
90      };
91    };
92  - |
93    spi {
94      #address-cells = <1>;
95      #size-cells = <0>;
96
97      dpll@70 {
98        compatible = "microchip,zl30731";
99        reg = <0x70>;
100        spi-max-frequency = <12500000>;
101
102        dpll-types = "pps";
103
104        input-pins {
105          #address-cells = <1>;
106          #size-cells = <0>;
107
108          sync1: pin@0 { /* REF0P - 1 PPS sync source */
109            reg = <0>;
110            connection-type = "gnss";
111            label = "GNSS_1PPS_IN";
112            supported-frequencies-hz = /bits/ 64 <1>;
113          };
114
115          pin@1 { /* REF0N - clock source */
116            reg = <1>;
117            connection-type = "gnss";
118            label = "GNSS_10M_IN";
119            supported-frequencies-hz = /bits/ 64 <10000000>;
120            ref-sync-sources = <&sync1>;
121          };
122        };
123
124        output-pins {
125          #address-cells = <1>;
126          #size-cells = <0>;
127
128          pin@3 { /* OUT1N */
129            reg = <3>;
130            connection-type = "gnss";
131            esync-control;
132            label = "Output 1";
133            supported-frequencies-hz = /bits/ 64 <1 10000>;
134          };
135        };
136      };
137    };
138...
139