Home
last modified time | relevance | path

Searched full:gmu (Results 1 – 6 of 6) sorted by relevance

/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_hfi.c31 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
47 * If we are to assume that the GMU firmware is in fact a rational actor in a6xx_hfi_queue_read()
62 if (!gmu->legacy) in a6xx_hfi_queue_read()
72 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
96 if (!gmu->legacy) { in a6xx_hfi_queue_write()
107 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
111 static int a6xx_hfi_wait_for_msg_interrupt(struct a6xx_gmu *gmu, u32 id, u32 seqnum) in a6xx_hfi_wait_for_msg_interrupt() argument
115 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_hfi_wait_for_msg_interrupt()
119 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_msg_interrupt()
128 /* We may timeout because the GMU is temporarily wedged from in a6xx_hfi_wait_for_msg_interrupt()
[all …]
H A Da6xx_gpu_state.h345 /* GMU GX */
354 /* GMU CX */
364 /* GMU AO */
/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,ocmem.yaml120 gmu-sram@0 {
/linux/arch/arm64/boot/dts/qcom/
H A Dsm8250-xiaomi-pipa.dts409 &gmu {
H A Dsa8295p-adp.dts335 &gmu {
H A Dsm8250-mtp.dts481 &gmu {