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/linux/Documentation/devicetree/bindings/display/msm/
H A Dgmu.yaml6 $id: http://devicetree.org/schemas/display/msm/gmu.yaml#
9 title: GMU attached to certain Adreno GPUs
15 These bindings describe the Graphics Management Unit (GMU) that is attached
16 to members of the Adreno A6xx GPU family. The GMU provides on-device power
24 - pattern: '^qcom,adreno-gmu-[6-8][0-9][0-9]\.[0-9]$'
25 - const: qcom,adreno-gmu
27 - pattern: '^qcom,adreno-gmu-x[1-9][0-9][0-9]\.[0-9]$'
28 - const: qcom,adreno-gmu
29 - const: qcom,adreno-gmu-wrapper
49 - description: GMU HFI interrupt
[all …]
/linux/drivers/gpu/drm/msm/adreno/
H A Da6xx_gmu.h35 * These define the different GMU wake up options - these define how both the
36 * CPU and the GMU bring up the hardware
39 /* THe GMU has already been booted and the rentention registers are active */
42 /* the GMU is coming up for the first time or back from a power collapse */
46 * These define the level of control that the GMU has - the higher the number
47 * the more things that the GMU hardware controls on its own.
50 /* The GMU does not do any idle state management */
56 /* The GMU manages SPTP power collapse */
59 /* The GMU does automatic IFPC (intra-frame power collapse) */
65 /* For serializing communication with the GMU: */
[all …]
H A Da6xx_hfi.c31 static int a6xx_hfi_queue_read(struct a6xx_gmu *gmu, in a6xx_hfi_queue_read() argument
47 * If we are to assume that the GMU firmware is in fact a rational actor in a6xx_hfi_queue_read()
62 if (!gmu->legacy) in a6xx_hfi_queue_read()
69 static int a6xx_hfi_queue_write(struct a6xx_gmu *gmu, in a6xx_hfi_queue_write() argument
93 if (!gmu->legacy) { in a6xx_hfi_queue_write()
101 gmu_write(gmu, REG_A6XX_GMU_HOST2GMU_INTR_SET, 0x01); in a6xx_hfi_queue_write()
105 static int a6xx_hfi_wait_for_msg_interrupt(struct a6xx_gmu *gmu, u32 id, u32 seqnum) in a6xx_hfi_wait_for_msg_interrupt() argument
109 struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu); in a6xx_hfi_wait_for_msg_interrupt()
113 ret = gmu_poll_timeout(gmu, REG_A6XX_GMU_GMU2HOST_INTR_INFO, val, in a6xx_hfi_wait_for_msg_interrupt()
122 /* We may timeout because the GMU is temporarily wedged from in a6xx_hfi_wait_for_msg_interrupt()
[all …]
H A Da6xx_gpu.c24 count_hi = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in read_gmu_ao_counter()
25 count_lo = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_L); in read_gmu_ao_counter()
26 temp = gmu_read(&a6xx_gpu->gmu, REG_A6XX_GMU_ALWAYS_ON_COUNTER_H); in read_gmu_ao_counter()
54 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in fenced_write() local
59 /* Nothing else to be done in the case of no-GMU */ in fenced_write()
68 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, in fenced_write()
76 if (!gmu_poll_timeout(gmu, REG_A6XX_GMU_AHB_FENCE_STATUS, status, in fenced_write()
83 dev_err_ratelimited(gmu->dev, "delay in fenced register write (0x%x)\n", in fenced_write()
88 dev_err_ratelimited(gmu->dev, "fenced register write (0x%x) fail\n", in fenced_write()
115 /* Check that the GMU is idle */ in _a6xx_check_idle()
[all …]
H A Da8xx_gpu.c125 /* Check that the GMU is idle */ in _a8xx_check_idle()
126 if (!a6xx_gmu_isidle(&a6xx_gpu->gmu)) in _a8xx_check_idle()
190 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a8xx_set_hwcg() local
196 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, in a8xx_set_hwcg()
198 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, in a8xx_set_hwcg()
200 gmu_write(gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, in a8xx_set_hwcg()
218 * GMU enables clk gating in GBIF during boot up. So, in a8xx_set_hwcg()
508 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in hw_init() local
514 ret = a6xx_gmu_set_oob(&a6xx_gpu->gmu, GMU_OOB_GPU_SET); in hw_init()
559 gmu_write(&a6xx_gpu->gmu, REG_A8XX_GMU_CX_GMU_POWER_COUNTER_SELECT_XOCLK_1, in hw_init()
[all …]
H A Da6xx_gpu_state.c155 if (!a6xx_gmu_sptprac_is_on(&a6xx_gpu->gmu)) in a6xx_crashdumper_run()
1189 /* Read a block of GMU registers */
1198 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in _a6xx_get_gmu_registers() local
1218 val = gmu_read_rscc(gmu, offset); in _a6xx_get_gmu_registers()
1220 val = gmu_read(gmu, offset); in _a6xx_get_gmu_registers()
1241 /* Get the CX GMU registers from AHB */ in a6xx_get_gmu_registers()
1254 if (!a6xx_gmu_gx_is_on(&a6xx_gpu->gmu)) in a6xx_get_gmu_registers()
1258 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_AO_AHB_FENCE_CTRL, 0); in a6xx_get_gmu_registers()
1292 struct a6xx_gmu *gmu = &a6xx_gpu->gmu; in a6xx_snapshot_gmu_hfi_history() local
1295 BUILD_BUG_ON(ARRAY_SIZE(gmu->queues) != ARRAY_SIZE(a6xx_state->hfi_queue_history)); in a6xx_snapshot_gmu_hfi_history()
[all …]
H A Da6xx_gpu.h92 struct a6xx_gmu gmu; member
264 int a6xx_gmu_wait_for_idle(struct a6xx_gmu *gmu);
266 bool a6xx_gmu_isidle(struct a6xx_gmu *gmu);
268 int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
269 void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state);
H A Da6xx_hfi.h49 /* This is the outgoing queue to the GMU */
52 /* THis is the incoming response queue from the GMU */
H A Da6xx_gpu_state.h345 /* GMU GX */
354 /* GMU CX */
364 /* GMU AO */
H A Da6xx_preempt.c151 gmu_write(&a6xx_gpu->gmu, REG_A6XX_GMU_PWR_COL_PREEMPT_KEEPALIVE, on); in a6xx_preempt_keepalive_vote()
/linux/arch/arm64/boot/dts/qcom/
H A Dpurwa.dtsi29 &gmu {
30 compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu";
H A Dsm8350.dtsi2049 qcom,gmu = <&gmu>;
2114 gmu: gmu@3d6a000 { label
2115 compatible = "qcom,adreno-gmu-660.1", "qcom,adreno-gmu";
2120 reg-names = "gmu", "rscc", "gmu_pdc";
2124 interrupt-names = "hfi", "gmu";
2133 clock-names = "gmu",
H A Dsc8180x.dtsi2277 qcom,gmu = <&gmu>;
2326 gmu: gmu@2c6a000 { label
2327 compatible = "qcom,adreno-gmu-680.1", "qcom,adreno-gmu";
2332 reg-names = "gmu",
2338 interrupt-names = "hfi", "gmu";
2345 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsc7180.dtsi2178 qcom,gmu = <&gmu>;
2276 gmu: gmu@506a000 { label
2277 compatible = "qcom,adreno-gmu-618.0", "qcom,adreno-gmu";
2280 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
2283 interrupt-names = "hfi", "gmu";
2288 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsm8450.dtsi2457 qcom,gmu = <&gmu>;
2531 gmu: gmu@3d6a000 { label
2532 compatible = "qcom,adreno-gmu-730.1", "qcom,adreno-gmu";
2536 reg-names = "gmu", "rscc", "gmu_pdc";
2540 interrupt-names = "hfi", "gmu";
2550 "gmu",
2632 clock-names = "gmu",
H A Dsdm845.dtsi4888 * controlled entirely by the GMU
4897 qcom,gmu = <&gmu>;
4978 gmu: gmu@506a000 { label
4979 compatible = "qcom,adreno-gmu-630.2", "qcom,adreno-gmu";
4984 reg-names = "gmu", "gmu_pdc", "gmu_pdc_seq";
4988 interrupt-names = "hfi", "gmu";
4994 clock-names = "gmu", "cxo", "axi", "memnoc";
H A Dsm8250-xiaomi-pipa.dts409 &gmu {
H A Dsm8250.dtsi2939 qcom,gmu = <&gmu>;
2998 gmu: gmu@3d6a000 { label
2999 compatible = "qcom,adreno-gmu-650.2", "qcom,adreno-gmu";
3005 reg-names = "gmu", "rscc", "gmu_pdc", "gmu_pdc_seq";
3009 interrupt-names = "hfi", "gmu";
3016 clock-names = "ahb", "gmu", "cxo", "axi", "memnoc";
H A Dsm8550.dtsi2485 qcom,gmu = <&gmu>;
2552 gmu: gmu@3d6a000 { label
2553 compatible = "qcom,adreno-gmu-740.1", "qcom,adreno-gmu";
2557 reg-names = "gmu", "rscc", "gmu_pdc";
2561 interrupt-names = "hfi", "gmu";
2571 "gmu",
H A Dsc8280xp.dtsi3367 qcom,gmu = <&gmu>;
3431 gmu: gmu@3d6a000 { label
3432 compatible = "qcom,adreno-gmu-690.0", "qcom,adreno-gmu";
3436 reg-names = "gmu", "rscc", "gmu_pdc";
3439 interrupt-names = "hfi", "gmu";
3447 clock-names = "gmu",
H A Dsa8295p-adp.dts335 &gmu {
H A Dsm8650.dtsi4152 qcom,gmu = <&gmu>;
4249 gmu: gmu@3d6a000 { label
4250 compatible = "qcom,adreno-gmu-750.1", "qcom,adreno-gmu";
4254 reg-names = "gmu", "rscc", "gmu_pdc";
4258 interrupt-names = "hfi", "gmu";
4268 "gmu",
H A Dsm8250-xiaomi-elish-common.dtsi539 &gmu {
/linux/Documentation/devicetree/bindings/sram/
H A Dqcom,ocmem.yaml120 gmu-sram@0 {
/linux/Documentation/devicetree/bindings/iommu/
H A Darm,smmu.yaml518 - const: gmu
527 - description: GMU clock

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