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/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Darm,gic-v3.yaml76 - GIC Redistributors (GICR), one range per redistributor region
178 GICR registers when the GIC redistributors are powered off.
248 <0x2f100000 0x200000>, // GICR
276 <0x2d000000 0x800000>, // GICR 1: CPUs 0-31
277 <0x2e000000 0x800000>, // GICR 2: CPUs 32-63
/linux/drivers/irqchip/
H A Dirq-gic-v3.c1898 /* Find the chips based on GICR regions PHYS addr */ in gic_enable_quirk_nvidia_t241()
2343 rdist_regs[i].redist_base = gic_of_iomap(node, 1 + i, "GICR", &res); in gic_of_init()
2414 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
2422 gic_request_region(redist->base_address, redist->length, "GICR"); in gic_acpi_parse_madt_redist()
2445 * Virtual hotplug systems can use the MADT's "always-on" GICR entries. in gic_acpi_parse_madt_gicc()
2460 gic_request_region(gicc->gicr_base_address, size, "GICR"); in gic_acpi_parse_madt_gicc()
2483 /* Collect redistributor base addresses in GICR entries */ in gic_acpi_collect_gicr_base()
2487 pr_info("No valid GICR entries exist\n"); in gic_acpi_collect_gicr_base()
2505 * If GICC is enabled and has valid gicr base address, then it means in gic_acpi_match_gicc()
2506 * GICR base is presented via GICC. The redistributor is only known to in gic_acpi_match_gicc()
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/linux/arch/arm64/boot/dts/intel/
H A Dkeembay-soc.dtsi58 <0x0 0x20580000 0x0 0x80000>; /* GICR */
/linux/arch/arm64/boot/dts/marvell/
H A Darmada-ap810-ap0.dtsi58 <0x3060000 0x100000>, /* GICR */
/linux/Documentation/arch/arm64/
H A Dcpu-hotplug.rst66 ``enabled``. The 'always on' GICR structure must be used to describe the
/linux/arch/arm64/boot/dts/cavium/
H A Dthunder2-99xx.dtsi67 <0x04 0x01000000 0x0 0x1000000>; /* GICR */
H A Dthunder-88xx.dtsi389 <0x8010 0x80000000 0x0 0x600000>; /* GICR */
/linux/arch/arm64/include/asm/
H A Dacpi.h64 #define CPUIDLE_GICR_CTXT BIT(2) /* GICR */
/linux/arch/arm64/boot/dts/amd/
H A Delba.dtsi147 <0x0 0xa00000 0x0 0x200000>, /* GICR */
/linux/arch/arm64/boot/dts/sprd/
H A Dums9620.dtsi174 <0x0 0x12040000 0 0x100000>; /* GICR */
H A Dums512.dtsi166 <0x0 0x12040000 0 0x100000>; /* GICR */
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhip05.dtsi247 <0x0 0x8d100000 0 0x300000>, /* GICR */
H A Dhip07.dtsi950 <0x0 0x4d100000 0x0 0x400000>, /* p0 GICR node 0 */
951 <0x0 0x6d100000 0x0 0x400000>, /* p0 GICR node 1 */
952 <0x400 0x4d100000 0x0 0x400000>, /* p1 GICR node 2 */
953 <0x400 0x6d100000 0x0 0x400000>, /* p1 GICR node 3 */
H A Dhip06.dtsi247 <0x0 0x4d100000 0 0x300000>, /* GICR */
/linux/arch/arm64/boot/dts/arm/
H A Dmorello.dtsi230 <0x0 0x300c0000 0x0 0x80000>; /* GICR */
H A Dfvp-base-revc.dts230 <0x0 0x2f100000 0 0x200000>, // GICR
/linux/arch/arm64/boot/dts/microchip/
H A Dsparx5.dtsi117 <0x6 0x00340000 0xc0000>, /* GICR */
/linux/arch/arm64/boot/dts/socionext/
H A Duniphier-ld11.dtsi601 <0x5fe40000 0x80000>; /* GICR */
/linux/arch/arm64/boot/dts/broadcom/stingray/
H A Dstingray.dtsi182 <0x02e00000 0x600000>; /* GICR */
/linux/arch/arm64/boot/dts/qcom/
H A Dsm4450.dtsi504 <0x0 0x17260000 0x0 0x100000>; /* GICR * 8 */
H A Dqdu1000.dtsi1438 <0x0 0x17260000 0x0 0x80000>; /* GICR * 4 */
/linux/arch/arm64/boot/dts/freescale/
H A Dimx8ulp.dtsi80 <0x0 0x2d440000 0 0xc0000>; /* GICR (RD_base + SGI_base) */
H A Dfsl-ls1088a.dtsi117 <0x0 0x06100000 0 0x100000>, /* GICR(RD_base+SGI_base)*/
H A Dfsl-ls208xa.dtsi52 <0x0 0x06100000 0 0x100000>, /* GICR (RD_base + SGI_base) */
/linux/arch/arm64/boot/dts/mediatek/
H A Dmt8365.dtsi287 <0 0x0c080000 0 0x80000>, /* GICR */

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