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Searched full:gcc_pcie_0_slv_q2a_axi_clk (Results 1 – 25 of 38) sorted by relevance

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/linux/include/dt-bindings/clock/
H A Dqcom,qdu1000-gcc.h55 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 macro
H A Dqcom,sm7150-gcc.h60 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 macro
H A Dqcom,gcc-sm6350.h72 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 61 macro
H A Dqcom,sar2130p-gcc.h50 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 40 macro
H A Dqcom,sm4450-gcc.h67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 macro
H A Dqcom,gcc-sc7280.h59 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 49 macro
H A Dqcom,sm8550-gcc.h54 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 43 macro
H A Dqcom,qcs8300-gcc.h75 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 65 macro
H A Dqcom,gcc-sdm845.h58 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 48 macro
H A Dqcom,gcc-sm8150.h67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 macro
H A Dqcom,sm8650-gcc.h56 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 45 macro
H A Dqcom,gcc-sm8450.h69 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 57 macro
H A Dqcom,gcc-sm8350.h67 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 macro
H A Dqcom,gcc-sm8250.h65 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 55 macro
H A Dqcom,sa8775p-gcc.h90 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 79 macro
H A Dqcom,gcc-sc8180x.h66 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 56 macro
H A Dqcom,gcc-sc8280xp.h106 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 95 macro
H A Dqcom,x1e80100-gcc.h77 #define GCC_PCIE_0_SLV_Q2A_AXI_CLK 67 macro
/linux/Documentation/devicetree/bindings/pci/
H A Dqcom,pcie-sm8350.yaml113 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
H A Dqcom,pcie-sc8180x.yaml118 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
H A Dqcom,pcie-sa8775p.yaml116 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>;
H A Dqcom,pcie-sm8150.yaml112 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
H A Dqcom,pcie-sm8250.yaml125 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
/linux/drivers/clk/qcom/
H A Dgcc-sar2130p.c1228 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { variable
1235 .name = "gcc_pcie_0_slv_q2a_axi_clk",
2156 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,
H A Dgcc-qdu1000.c1573 static struct clk_branch gcc_pcie_0_slv_q2a_axi_clk = { variable
1582 .name = "gcc_pcie_0_slv_q2a_axi_clk",
2493 [GCC_PCIE_0_SLV_Q2A_AXI_CLK] = &gcc_pcie_0_slv_q2a_axi_clk.clkr,

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