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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_gart.c42 * GART
43 * The GART (Graphics Aperture Remapping Table) is an aperture
49 * Radeon GPUs support both an internal GART, as described above,
50 * and AGP. AGP works similarly, but the GART table is configured
55 * Both AGP and internal GART can be used at the same time, however
58 * This file handles the common internal GART management.
62 * Common GART table functions.
71 * This dummy page is used by the driver as a filler for gart entries
72 * when pages are taken out of the GART
110 * amdgpu_gart_table_ram_alloc - allocate system ram for gart page table
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H A Damdgpu_gtt_mgr.c106 * amdgpu_gtt_mgr_mark_bo_teardown - exclude a BO from GART recovery
110 * Keep the GART range allocated until the resource is freed, but make recovery
209 * amdgpu_gtt_mgr_alloc_entries - alloc GART entries without GTT bo
216 * Helper to dynamic alloc GART entries to map memory not accociated with
244 * amdgpu_gtt_mgr_free_entries - free GART entries not accocaited with GTT bo
259 * amdgpu_gtt_mgr_recover - re-init gart
263 * Re-init the gart for each known BO in the GTT.
291 * Simplified intersection test, only interesting if we need GART or not.
H A Dgmc_v11_0.c211 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
226 /* Use register 17 for GART */ in gmc_v11_0_flush_gpu_tlb()
680 * vram and gart within the GPU's physical address space.
711 /* set the gart size */ in gmc_v11_0_mc_init()
723 if (adev->gart.bo) { in gmc_v11_0_gart_init()
724 WARN(1, "PCIE GART already initialized\n"); in gmc_v11_0_gart_init()
728 /* Initialize common gart structure */ in gmc_v11_0_gart_init()
733 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v11_0_gart_init()
734 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | in gmc_v11_0_gart_init()
869 * Tears down the driver GART/VM setup (CIK).
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H A Damdgpu_gmc.c171 * The following is for PTE only. GART does not have PDEs. in amdgpu_gmc_set_pte_pde()
240 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
245 * This function is only used if use GART for FB translation. In such
247 * and gart (aka system memory) access.
254 * address 0. So vram start at address 0 and gart is right after vram.
267 * amdgpu_bo_create_reserved() from FB aperture to GART aperture. in amdgpu_gmc_sysvm_location()
279 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", in amdgpu_gmc_sysvm_location()
293 * amdgpu_gmc_gart_location - try to find GART location
297 * @gart_placement: GART placement policy with respect to VRAM
299 * Function will try to place GART befor
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H A Dgfxhub_v1_0.c61 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_0_init_gart_aperture_regs()
65 /* If use GART for FB translation, vmid0 page table covers both in gfxhub_v1_0_init_gart_aperture_regs()
66 * vram and system memory (gart) in gfxhub_v1_0_init_gart_aperture_regs()
141 /* In the case squeezing vram into GART aperture, we don't use in gfxhub_v1_0_init_system_aperture_regs()
325 /* GART Enable. */ in gfxhub_v1_0_gart_enable()
371 * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
H A Damdgpu_isp.c163 * GART alloc to generate GPU addr for BO to make it accessible through the
164 * GART aperture for ISP HW.
206 drm_err(&adev->ddev, "failed to alloc gart user buffer (%d)", ret); in isp_user_buffer_alloc()
293 drm_err(&adev->ddev, "failed to alloc gart kernel buffer (%d)", ret); in isp_kernel_buffer_alloc()
H A Damdgpu_gart.h30 * GART structures, functions & helpers
44 /* CPU kmapped address of gart table */
H A Dgfxhub_v1_2.c85 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v1_2_xcc_init_gart_aperture_regs()
89 /* If use GART for FB translation, vmid0 page table covers both in gfxhub_v1_2_xcc_init_gart_aperture_regs()
90 * vram and system memory (gart) in gfxhub_v1_2_xcc_init_gart_aperture_regs()
182 /* In the case squeezing vram into GART aperture, we don't use in gfxhub_v1_2_xcc_init_system_aperture_regs()
421 /* GART Enable. */ in gfxhub_v1_2_xcc_gart_enable()
528 * gfxhub_v1_2_set_fault_enable_default - update GART/VM fault handling
H A Damdgpu_ttm.h94 /* @default_entity: for workarounds, has no gart windows */
223 * amdgpu_compute_gart_address() - Returns GART address of an entity's window
225 * @entity: The &struct amdgpu_ttm_buffer_entity owning the GART window
H A Dgfxhub_v12_1.c102 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v12_1_xcc_init_gart_aperture_regs()
106 /* If use GART for FB translation, vmid0 page table covers both in gfxhub_v12_1_xcc_init_gart_aperture_regs()
107 * vram and system memory (gart) in gfxhub_v12_1_xcc_init_gart_aperture_regs()
517 /* GART Enable. */ in gfxhub_v12_1_xcc_gart_enable()
653 * gfxhub_v12_1_set_fault_enable_default - update GART/VM fault handling
H A Dgfxhub_v2_0.c136 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v2_0_init_gart_aperture_regs()
347 /* GART Enable. */ in gfxhub_v2_0_gart_enable()
387 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
/linux/drivers/gpu/drm/radeon/
H A Drs400.c45 /* Check gart size */ in rs400_gart_adjust_size()
56 DRM_ERROR("Unable to use IGP GART size %uM\n", in rs400_gart_adjust_size()
58 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); in rs400_gart_adjust_size()
59 DRM_ERROR("Forcing to 32M GART size\n"); in rs400_gart_adjust_size()
85 if (rdev->gart.ptr) { in rs400_gart_init()
86 WARN(1, "RS400 GART already initialized\n"); in rs400_gart_init()
89 /* Check gart size */ in rs400_gart_init()
102 /* Initialize common gart structure */ in rs400_gart_init()
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
119 /* Check gart size */ in rs400_gart_enable()
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H A Dradeon_drv.h61 * 1.6 - Add static GART memory manager
65 * Add GART offset query for getparam
94 * 1.19- Add support for gart table in FB memory and PCIE r300
102 * 1.26- Add support for variable size PCI(E) gart aperture
103 * 1.27- Add support for IGP GART
H A Drs600.c34 * R4XX family. The GART is different from the RS400 one and is very
36 * of the RS600 GART block).
525 * GART.
549 if (rdev->gart.robj) { in rs600_gart_init()
550 WARN(1, "RS600 GART already initialized\n"); in rs600_gart_init()
553 /* Initialize common gart structure */ in rs600_gart_init()
558 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
567 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
568 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
604 rdev->gart.table_addr); in rs600_gart_enable()
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H A Dradeon_asic.c151 * Removes AGP flags and changes the gart callbacks on AGP
152 * cards when using the internal gart rather than AGP (all asics).
166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in radeon_agp_disable()
167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in radeon_agp_disable()
168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in radeon_agp_disable()
172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in radeon_agp_disable()
173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in radeon_agp_disable()
174 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in radeon_agp_disable()
208 .gart = {
276 .gart = {
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H A Dr300.c83 * rv370,rv380 PCIE GART
122 void __iomem *ptr = rdev->gart.ptr; in rv370_pcie_gart_set_page()
134 if (rdev->gart.robj) { in rv370_pcie_gart_init()
135 WARN(1, "RV370 PCIE GART already initialized\n"); in rv370_pcie_gart_init()
138 /* Initialize common gart structure */ in rv370_pcie_gart_init()
144 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rv370_pcie_gart_init()
145 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in rv370_pcie_gart_init()
146 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in rv370_pcie_gart_init()
147 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in rv370_pcie_gart_init()
157 if (rdev->gart.robj == NULL) { in rv370_pcie_gart_enable()
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/linux/arch/x86/kernel/
H A Damd_gart_64.c5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
39 #include <asm/gart.h>
45 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
53 * of only flushing when an mapping is reused. With it true the GART is
79 /* GART can only remap to physical addresses < 1TB */
87 static bool need_flush; /* global flush state. set for each gart wrap */
259 * This driver will not always use a GART mapping, but might have in gart_unmap_phys()
554 /* Flush the GART-TLB to remove stale entries */ in enable_gart_translations()
583 pr_info("PCI-DMA: Restoring GART aperture settings\n"); in gart_fixup_northbridges()
599 pr_info("PCI-DMA: Resuming GART IOMMU\n"); in gart_resume()
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/linux/arch/x86/include/asm/
H A Dgart.h23 /* GART cache control register bits. */
27 /* K8 On-cpu GART registers */
66 * Don't enable translation but enable GART IO and CPU accesses. in gart_set_size_and_enable()
67 * Also, set DISTLBWALKPRB since GART tables memory is UC. in gart_set_size_and_enable()
84 /* Enable GART translation for this hammer. */ in enable_gart_translation()
H A Dagp.h10 * GART gives the CPU a physical alias of pages in memory. The alias
/linux/arch/powerpc/include/asm/
H A Duninorth.h53 * GART_BASE register appear to contain the physical address of the GART
55 * GART size in the low order bits (number of GART pages)
57 * The GART format itself is one 32bits word per physical memory page.
62 * Obviously, the GART is not cache coherent and so any change to it
63 * must be flushed to memory (or maybe just make the GART space non
66 * In order to invalidate the GART (which is probably necessary to inval
/linux/drivers/char/agp/
H A DKconfig14 If you need more texture memory than you can get with the AGP GART
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
116 This option gives you AGP GART support for the HP Quicksilver
H A Dparisc-agp.c3 * HP Quicksilver AGP GART routines
292 "GART disabled\n"); in agp_ioc_init()
435 MODULE_DESCRIPTION("HP Quicksilver AGP GART routines");
/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_chan.c109 nvif_object_dtor(&chan->gart); in nouveau_channel_del()
361 nouveau_channel_init(struct nouveau_channel *chan, u32 vram, u32 gart) in nouveau_channel_init() argument
394 /* allocate dma objects to cover all allowed vram, and gart */ in nouveau_channel_init()
432 ret = nvif_object_ctor(&chan->user, "abi16ChanGartCtxDma", gart, in nouveau_channel_init()
434 &chan->gart); in nouveau_channel_init()
502 bool priv, u64 runm, u32 vram, u32 gart, struct nouveau_channel **pchan) in nouveau_channel_new() argument
512 ret = nouveau_channel_init(*pchan, vram, gart); in nouveau_channel_new()
/linux/include/uapi/drm/
H A Dradeon_drm.h317 /* There are 2 heaps (local/GART). Each region within a heap is a
704 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
710 #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
738 int __user *region_offset; /* offset from start of fb or GART */
773 #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
775 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
/linux/drivers/gpu/drm/omapdrm/
H A DTODO3 accessing the pages via a GART, so maybe we need some other threshold

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