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/linux/drivers/gpu/drm/radeon/
H A Drs400.c45 /* Check gart size */ in rs400_gart_adjust_size()
56 DRM_ERROR("Unable to use IGP GART size %uM\n", in rs400_gart_adjust_size()
58 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); in rs400_gart_adjust_size()
59 DRM_ERROR("Forcing to 32M GART size\n"); in rs400_gart_adjust_size()
85 if (rdev->gart.ptr) { in rs400_gart_init()
86 WARN(1, "RS400 GART already initialized\n"); in rs400_gart_init()
89 /* Check gart size */ in rs400_gart_init()
102 /* Initialize common gart structure */ in rs400_gart_init()
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
119 /* Check gart size */ in rs400_gart_enable()
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H A Dradeon_drv.h61 * 1.6 - Add static GART memory manager
65 * Add GART offset query for getparam
94 * 1.19- Add support for gart table in FB memory and PCIE r300
102 * 1.26- Add support for variable size PCI(E) gart aperture
103 * 1.27- Add support for IGP GART
H A Drs600.c34 * R4XX family. The GART is different from the RS400 one and is very
36 * of the RS600 GART block).
525 * GART.
549 if (rdev->gart.robj) { in rs600_gart_init()
550 WARN(1, "RS600 GART already initialized\n"); in rs600_gart_init()
553 /* Initialize common gart structure */ in rs600_gart_init()
558 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
567 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
568 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
604 rdev->gart.table_addr); in rs600_gart_enable()
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H A Dradeon_asic.c151 * Removes AGP flags and changes the gart callbacks on AGP
152 * cards when using the internal gart rather than AGP (all asics).
166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in radeon_agp_disable()
167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in radeon_agp_disable()
168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in radeon_agp_disable()
172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in radeon_agp_disable()
173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in radeon_agp_disable()
174 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in radeon_agp_disable()
208 .gart = {
276 .gart = {
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra20-mc.yaml21 Tegra20 Memory Controller includes the GART (Graphics Address Relocation
27 const: nvidia,tegra20-mc-gart
32 - description: GART registers
68 compatible = "nvidia,tegra20-mc-gart";
70 <0x58000000 0x02000000>; /* GART aperture */
/linux/arch/x86/kernel/
H A Damd_gart_64.c5 * Use the integrated AGP GART in the Hammer northbridge as an IOMMU for PCI.
39 #include <asm/gart.h>
45 static unsigned long iommu_bus_base; /* GART remapping area (physical) */
53 * of only flushing when an mapping is reused. With it true the GART is
79 /* GART can only remap to physical addresses < 1TB */
87 static bool need_flush; /* global flush state. set for each gart wrap */
258 * This driver will not always use a GART mapping, but might have in gart_unmap_phys()
552 /* Flush the GART-TLB to remove stale entries */ in enable_gart_translations()
581 pr_info("PCI-DMA: Restoring GART aperture settings\n"); in gart_fixup_northbridges()
597 pr_info("PCI-DMA: Resuming GART IOMMU\n"); in gart_resume()
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/linux/arch/x86/include/asm/
H A Dgart.h23 /* GART cache control register bits. */
27 /* K8 On-cpu GART registers */
66 * Don't enable translation but enable GART IO and CPU accesses. in gart_set_size_and_enable()
67 * Also, set DISTLBWALKPRB since GART tables memory is UC. in gart_set_size_and_enable()
84 /* Enable GART translation for this hammer. */ in enable_gart_translation()
H A Dagp.h10 * GART gives the CPU a physical alias of pages in memory. The alias
/linux/arch/powerpc/include/asm/
H A Duninorth.h53 * GART_BASE register appear to contain the physical address of the GART
55 * GART size in the low order bits (number of GART pages)
57 * The GART format itself is one 32bits word per physical memory page.
62 * Obviously, the GART is not cache coherent and so any change to it
63 * must be flushed to memory (or maybe just make the GART space non
66 * In order to invalidate the GART (which is probably necessary to inval
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v12_0.c221 * GART
234 /* Use register 17 for GART */ in gmc_v12_0_flush_vm_hub()
310 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback
705 * vram and gart within the GPU's physical address space.
737 /* set the gart size */ in gmc_v12_0_mc_init()
752 if (adev->gart.bo) { in gmc_v12_0_gart_init()
753 WARN(1, "PCIE GART already initialized\n"); in gmc_v12_0_gart_init()
757 /* Initialize common gart structure */ in gmc_v12_0_gart_init()
762 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v12_0_gart_init()
763 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | in gmc_v12_0_gart_init()
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H A Dgmc_v11_0.c228 * gmc_v11_0_flush_gpu_tlb - gart tlb flush callback
243 /* Use register 17 for GART */ in gmc_v11_0_flush_gpu_tlb()
695 * vram and gart within the GPU's physical address space.
726 /* set the gart size */ in gmc_v11_0_mc_init()
741 if (adev->gart.bo) { in gmc_v11_0_gart_init()
742 WARN(1, "PCIE GART already initialized\n"); in gmc_v11_0_gart_init()
746 /* Initialize common gart structure */ in gmc_v11_0_gart_init()
751 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v11_0_gart_init()
752 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | in gmc_v11_0_gart_init()
884 * Tears down the driver GART/VM setup (CIK).
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H A Dgmc_v10_0.c236 * GART
243 * gmc_v10_0_flush_gpu_tlb - gart tlb flush callback
258 /* Use register 17 for GART */ in gmc_v10_0_flush_gpu_tlb()
697 * vram and gart within the GPU's physical address space.
726 /* set the gart size */ in gmc_v10_0_mc_init()
752 if (adev->gart.bo) { in gmc_v10_0_gart_init()
753 WARN(1, "NAVI10 PCIE GART already initialized\n"); in gmc_v10_0_gart_init()
757 /* Initialize common gart structure */ in gmc_v10_0_gart_init()
762 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v10_0_gart_init()
763 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_NV10(0ULL, MTYPE_UC) | in gmc_v10_0_gart_init()
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H A Damdgpu_gmc.c170 * The following is for PTE only. GART does not have PDEs. in amdgpu_gmc_set_pte_pde()
239 /** amdgpu_gmc_sysvm_location - place vram and gart in sysvm aperture
244 * This function is only used if use GART for FB translation. In such
246 * and gart (aka system memory) access.
253 * address 0. So vram start at address 0 and gart is right after vram.
266 * amdgpu_bo_create_reserved() from FB aperture to GART aperture. in amdgpu_gmc_sysvm_location()
278 dev_info(adev->dev, "GART: %lluM 0x%016llX - 0x%016llX\n", in amdgpu_gmc_sysvm_location()
283 * amdgpu_gmc_gart_location - try to find GART location
287 * @gart_placement: GART placement policy with respect to VRAM
289 * Function will try to place GART before or after VRAM.
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H A Dgmc_v7_0.c255 * Set the location of vram, gart, and AGP in the GPU's
321 * vram and gart within the GPU's physical address space (CIK).
396 /* set the gart size */ in gmc_v7_0_mc_init()
454 * GART
461 * gmc_v7_0_flush_gpu_tlb - gart tlb flush callback
602 * gmc_v7_0_gart_enable - gart enable
618 if (adev->gart.bo == NULL) { in gmc_v7_0_gart_enable()
619 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v7_0_gart_enable()
623 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in gmc_v7_0_gart_enable()
708 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v7_0_gart_enable()
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H A Damdgpu_gmc.h219 * gart/vram_start/end field as the later is from
241 /* GART aperture start and end in MC address space
243 * to place GART by setting VM_CONTEXT0_PAGE_TABLE_START/END_ADDR
245 * Under VMID0, logical address inside GART aperture will
246 * be translated through gpuvm gart page table to access
257 * If driver uses GART table for VMID0 FB access, driver finds a hole in
259 * which the first part is vram and the second part is gart (covering
H A Dgmc_v8_0.c430 * Set the location of vram, gart, and AGP in the GPU's
507 * vram and gart within the GPU's physical address space (VI).
587 /* set the gart size */ in gmc_v8_0_mc_init()
645 * GART
652 * gmc_v8_0_flush_gpu_tlb - gart tlb flush callback
819 * gmc_v8_0_gart_enable - gart enable
835 if (adev->gart.bo == NULL) { in gmc_v8_0_gart_enable()
836 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v8_0_gart_enable()
840 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in gmc_v8_0_gart_enable()
942 DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v8_0_gart_enable()
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H A Damdgpu_isp.c163 * GART alloc to generate GPU addr for BO to make it accessible through the
164 * GART aperture for ISP HW.
206 drm_err(&adev->ddev, "failed to alloc gart user buffer (%d)", ret); in isp_user_buffer_alloc()
293 drm_err(&adev->ddev, "failed to alloc gart kernel buffer (%d)", ret); in isp_kernel_buffer_alloc()
H A Dgmc_v6_0.c330 /* set the gart size */ in gmc_v6_0_mc_init()
477 if (adev->gart.bo == NULL) { in gmc_v6_0_gart_enable()
478 dev_err(adev->dev, "No VRAM object for PCIE GART.\n"); in gmc_v6_0_gart_enable()
483 table_addr = amdgpu_bo_gpu_offset(adev->gart.bo); in gmc_v6_0_gart_enable()
558 dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n", in gmc_v6_0_gart_enable()
568 if (adev->gart.bo) { in gmc_v6_0_gart_init()
569 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n"); in gmc_v6_0_gart_init()
575 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v6_0_gart_init()
576 adev->gart.gart_pte_flags = 0; in gmc_v6_0_gart_init()
H A Dgmc_v9_0.c819 * GART
1696 * vram and gart within the GPU's physical address space.
1749 /* set the gart size */ in gmc_v9_0_mc_init()
1784 if (adev->gart.bo) { in gmc_v9_0_gart_init()
1785 WARN(1, "VEGA10 PCIE GART already initialized\n"); in gmc_v9_0_gart_init()
1797 /* Initialize common gart structure */ in gmc_v9_0_gart_init()
1801 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v9_0_gart_init()
1802 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_VG10(0ULL, MTYPE_UC) | in gmc_v9_0_gart_init()
1806 dev_info(adev->dev, "Put GART in system memory for APU\n"); in gmc_v9_0_gart_init()
1809 dev_err(adev->dev, "Failed to allocate GART in system memory\n"); in gmc_v9_0_gart_init()
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H A Dmmhub_v3_3.c254 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v3_3_init_gart_aperture_regs()
472 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v3_3_init_saw_regs()
475 /* Program page table base, gart start, gart end */ in mmhub_v3_3_init_saw_regs()
515 /* GART Enable. */ in mmhub_v3_3_gart_enable()
561 * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling
H A Dmes_userqueue.c46 DRM_ERROR("Failed to bind bo to GART. ret %d\n", ret); in mes_userq_map_gtt_bo_to_gart()
86 DRM_ERROR("Requested GART mapping for wptr bo larger than one page\n"); in mes_userq_create_wptr_mapping()
92 DRM_ERROR("Failed to map wptr bo to GART\n"); in mes_userq_create_wptr_mapping()
393 /* FW expects WPTR BOs to be mapped into GART */ in mes_userq_mqd_create()
/linux/drivers/char/agp/
H A DKconfig14 If you need more texture memory than you can get with the AGP GART
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
116 This option gives you AGP GART support for the HP Quicksilver
H A Dparisc-agp.c3 * HP Quicksilver AGP GART routines
292 "GART disabled\n"); in agp_ioc_init()
435 MODULE_DESCRIPTION("HP Quicksilver AGP GART routines");
/linux/include/uapi/drm/
H A Dradeon_drm.h317 /* There are 2 heaps (local/GART). Each region within a heap is a
704 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
710 #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
738 int __user *region_offset; /* offset from start of fb or GART */
773 #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
775 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
/linux/drivers/gpu/drm/omapdrm/
H A DTODO3 accessing the pages via a GART, so maybe we need some other threshold

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