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/linux/drivers/gpu/drm/radeon/
H A Drs400.c45 /* Check gart size */ in rs400_gart_adjust_size()
56 DRM_ERROR("Unable to use IGP GART size %uM\n", in rs400_gart_adjust_size()
58 DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); in rs400_gart_adjust_size()
59 DRM_ERROR("Forcing to 32M GART size\n"); in rs400_gart_adjust_size()
85 if (rdev->gart.ptr) { in rs400_gart_init()
86 WARN(1, "RS400 GART already initialized\n"); in rs400_gart_init()
89 /* Check gart size */ in rs400_gart_init()
102 /* Initialize common gart structure */ in rs400_gart_init()
107 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; in rs400_gart_init()
119 /* Check gart size */ in rs400_gart_enable()
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H A Dradeon_drv.h61 * 1.6 - Add static GART memory manager
65 * Add GART offset query for getparam
94 * 1.19- Add support for gart table in FB memory and PCIE r300
102 * 1.26- Add support for variable size PCI(E) gart aperture
103 * 1.27- Add support for IGP GART
H A Drs600.c34 * R4XX family. The GART is different from the RS400 one and is very
36 * of the RS600 GART block).
525 * GART.
549 if (rdev->gart.robj) { in rs600_gart_init()
550 WARN(1, "RS600 GART already initialized\n"); in rs600_gart_init()
553 /* Initialize common gart structure */ in rs600_gart_init()
558 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8; in rs600_gart_init()
567 if (rdev->gart.robj == NULL) { in rs600_gart_enable()
568 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); in rs600_gart_enable()
604 rdev->gart.table_addr); in rs600_gart_enable()
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H A Dradeon_asic.c151 * Removes AGP flags and changes the gart callbacks on AGP
152 * cards when using the internal gart rather than AGP (all asics).
166 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush; in radeon_agp_disable()
167 rdev->asic->gart.get_page_entry = &rv370_pcie_gart_get_page_entry; in radeon_agp_disable()
168 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page; in radeon_agp_disable()
172 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush; in radeon_agp_disable()
173 rdev->asic->gart.get_page_entry = &r100_pci_gart_get_page_entry; in radeon_agp_disable()
174 rdev->asic->gart.set_page = &r100_pci_gart_set_page; in radeon_agp_disable()
208 .gart = {
276 .gart = {
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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Dnvidia,tegra20-mc.yaml21 Tegra20 Memory Controller includes the GART (Graphics Address Relocation
27 const: nvidia,tegra20-mc-gart
32 - description: GART registers
68 compatible = "nvidia,tegra20-mc-gart";
70 <0x58000000 0x02000000>; /* GART aperture */
/linux/arch/x86/include/asm/
H A Dgart.h23 /* GART cache control register bits. */
27 /* K8 On-cpu GART registers */
66 * Don't enable translation but enable GART IO and CPU accesses. in gart_set_size_and_enable()
67 * Also, set DISTLBWALKPRB since GART tables memory is UC. in gart_set_size_and_enable()
84 /* Enable GART translation for this hammer. */ in enable_gart_translation()
H A Dagp.h10 * GART gives the CPU a physical alias of pages in memory. The alias
/linux/arch/powerpc/include/asm/
H A Duninorth.h53 * GART_BASE register appear to contain the physical address of the GART
55 * GART size in the low order bits (number of GART pages)
57 * The GART format itself is one 32bits word per physical memory page.
62 * Obviously, the GART is not cache coherent and so any change to it
63 * must be flushed to memory (or maybe just make the GART space non
66 * In order to invalidate the GART (which is probably necessary to inval
/linux/drivers/gpu/drm/amd/amdgpu/
H A Dgmc_v12_0.c192 * GART
205 /* Use register 17 for GART */ in gmc_v12_0_flush_vm_hub()
281 * gmc_v12_0_flush_gpu_tlb - gart tlb flush callback
678 * vram and gart within the GPU's physical address space.
710 /* set the gart size */ in gmc_v12_0_mc_init()
725 if (adev->gart.bo) { in gmc_v12_0_gart_init()
726 WARN(1, "PCIE GART already initialized\n"); in gmc_v12_0_gart_init()
730 /* Initialize common gart structure */ in gmc_v12_0_gart_init()
735 adev->gart.table_size = adev->gart.num_gpu_pages * 8; in gmc_v12_0_gart_init()
736 adev->gart.gart_pte_flags = AMDGPU_PTE_MTYPE_GFX12(0ULL, MTYPE_UC) | in gmc_v12_0_gart_init()
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H A Damdgpu_isp.c163 * GART alloc to generate GPU addr for BO to make it accessible through the
164 * GART aperture for ISP HW.
206 drm_err(&adev->ddev, "failed to alloc gart user buffer (%d)", ret); in isp_user_buffer_alloc()
291 drm_err(&adev->ddev, "failed to alloc gart kernel buffer (%d)", ret); in isp_kernel_buffer_alloc()
H A Damdgpu_gart.h30 * GART structures, functions & helpers
44 /* CPU kmapped address of gart table */
H A Dmmhub_v3_3.c254 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v3_3_init_gart_aperture_regs()
472 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v3_3_init_saw_regs()
475 /* Program page table base, gart start, gart end */ in mmhub_v3_3_init_saw_regs()
515 /* GART Enable. */ in mmhub_v3_3_gart_enable()
561 * mmhub_v3_3_set_fault_enable_default - update GART/VM fault handling
H A Damdgpu_gtt_mgr.c184 * amdgpu_gtt_mgr_recover - re-init gart
188 * Re-init the gart for each known BO in the GTT.
213 * Simplified intersection test, only interesting if we need GART or not.
H A Dgfxhub_v2_0.c136 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v2_0_init_gart_aperture_regs()
347 /* GART Enable. */ in gfxhub_v2_0_gart_enable()
387 * gfxhub_v2_0_set_fault_enable_default - update GART/VM fault handling
H A Dgfxhub_v3_0_3.c138 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v3_0_3_init_gart_aperture_regs()
359 /* GART Enable. */ in gfxhub_v3_0_3_gart_enable()
397 * gfxhub_v3_0_3_set_fault_enable_default - update GART/VM fault handling
H A Dgfxhub_v11_5_0.c140 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v11_5_0_init_gart_aperture_regs()
369 /* GART Enable. */ in gfxhub_v11_5_0_gart_enable()
407 * gfxhub_v11_5_0_set_fault_enable_default - update GART/VM fault handling
H A Dgfxhub_v3_0.c135 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v3_0_init_gart_aperture_regs()
366 /* GART Enable. */ in gfxhub_v3_0_gart_enable()
404 * gfxhub_v3_0_set_fault_enable_default - update GART/VM fault handling
H A Dgfxhub_v12_0.c143 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in gfxhub_v12_0_init_gart_aperture_regs()
374 /* GART Enable. */ in gfxhub_v12_0_gart_enable()
412 * gfxhub_v12_0_set_fault_enable_default - update GART/VM fault handling
H A Dmmhub_v1_0.c70 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v1_0_init_gart_aperture_regs()
234 uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); in mmhub_v1_0_init_saw()
376 /* GART Enable. */ in mmhub_v1_0_gart_enable()
420 * mmhub_v1_0_set_fault_enable_default - update GART/VM fault handling
/linux/drivers/char/agp/
H A DKconfig14 If you need more texture memory than you can get with the AGP GART
60 tristate "AMD Opteron/Athlon64 on-CPU GART support"
116 This option gives you AGP GART support for the HP Quicksilver
H A Dparisc-agp.c3 * HP Quicksilver AGP GART routines
292 "GART disabled\n"); in agp_ioc_init()
435 MODULE_DESCRIPTION("HP Quicksilver AGP GART routines");
/linux/include/uapi/drm/
H A Dradeon_drm.h317 /* There are 2 heaps (local/GART). Each region within a heap is a
704 #define RADEON_PARAM_GART_BUFFER_OFFSET 1 /* card offset of 1st GART buffer */
710 #define RADEON_PARAM_GART_BASE 6 /* card offset of GART base */
738 int __user *region_offset; /* offset from start of fb or GART */
773 #define RADEON_SETPARAM_PCIGART_LOCATION 3 /* PCI Gart Location */
775 #define RADEON_SETPARAM_PCIGART_TABLE_SIZE 5 /* PCI GART Table Size */
/linux/drivers/gpu/drm/omapdrm/
H A DTODO3 accessing the pages via a GART, so maybe we need some other threshold
/linux/arch/alpha/include/asm/
H A Dcore_irongate.h43 igcsr32 bar1; /* 0x14 - BAR1 - GART */
88 igcsr32 agpmode; /* 0xB0 - AGP/GART mode control */
/linux/drivers/gpu/drm/gma500/
H A Dgem.h26 int in_gart; /* Currently in the GART (ref ct) */

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