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/linux/arch/sparc/kernel/
H A Dktlb.S34 sethi %hi(PAGE_SIZE), %g5
35 cmp %g4, %g5
39 KERN_TSB_LOOKUP_TL1(%g4, %g6, %g5, %g1, %g2, %g3, kvmap_itlb_load)
42 sethi %hi(LOW_OBP_ADDRESS), %g5
43 cmp %g4, %g5
45 mov 0x1, %g5
46 sllx %g5, 32, %g5
47 cmp %g4, %g5
52 KERN_PGTABLE_WALK(%g4, %g5, %g2, kvmap_itlb_longpath)
55 TSB_WRITE(%g1, %g5, %g6)
[all …]
H A Dsun4v_tlb_miss.S55 LOAD_ITLB_INFO(%g2, %g4, %g5)
56 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_itlb_4v)
78 mov %o2, %g5 ! save %o2
88 mov %g5, %o2 ! restore %o2
101 LOAD_DTLB_INFO(%g2, %g4, %g5)
102 COMPUTE_TAG_TARGET(%g6, %g4, %g5, kvmap_dtlb_4v)
121 mov %o2, %g5 ! save %o2
131 mov %g5, %o2 ! restore %o2
139 /* Load MMU Miss base into %g5. */
140 ldxa [%g0] ASI_SCRATCHPAD, %g5
[all …]
H A Dsun4v_ivec.S31 sethi %hi(trap_block), %g5
32 or %g5, %lo(trap_block), %g5
33 sub %g4, %g5, %g3
37 sethi %hi(cpu_mondo_counter), %g5
38 or %g5, %lo(cpu_mondo_counter), %g5
40 add %g5, %g3, %g5
41 ldx [%g5], %g3
43 stx %g3, [%g5]
52 * high half is context arg to MMU flushes, into %g5
58 srlx %g3, 32, %g5
[all …]
H A Dtrampoline_32.S60 set current_set, %g5
63 ld [%g5 + %g4], %g6
75 set poke_srmmu, %g5
76 ld [%g5], %g5
77 call %g5
122 set current_set, %g5
124 ld [%g5 + %g4], %g6
136 set poke_srmmu, %g5
137 ld [%g5], %g5
138 call %g5
[all …]
H A Dtsb.S25 * %g5: available temporary
52 TRAP_LOAD_TRAP_BLOCK(%g7, %g5)
59 661: ldx [%g7 + TRAP_PER_CPU_TSB_HUGE], %g5
63 mov SCRATCHPAD_UTSBREG2, %g5
64 ldxa [%g5] ASI_SCRATCHPAD, %g5
67 cmp %g5, -1
79 and %g5, 0x7, %g6
81 andn %g5, 0x7, %g5
87 add %g5, %g6, %g5
89 TSB_LOAD_QUAD(%g5, %g6)
[all …]
H A Dtrampoline_64.S44 BRANCH_IF_CHEETAH_BASE(g1, g5, cheetah_startup)
45 BRANCH_IF_CHEETAH_PLUS_OR_FOLLOWON(g1, g5, cheetah_plus_startup)
59 sethi %uhi(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
60 or %g5, %ulo(DCU_ME|DCU_RE|DCU_HPE|DCU_SPE|DCU_SL|DCU_WE), %g5
61 sllx %g5, 32, %g5
62 or %g5, DCU_DM | DCU_IM | DCU_DC | DCU_IC, %g5
63 stxa %g5, [%g0] ASI_DCU_CONTROL_REG
85 sethi %hi(0x80000000), %g5
86 sllx %g5, 32, %g5
87 wr %g5, %asr25
[all …]
H A Dhead_32.S132 set current_pc, %g5
133 cmp %g3, %g5
262 lda [%g0] ASI_M_MMUREGS, %g5 ! DO NOT TOUCH %g5
264 or %g5, %g6, %g6 ! Or it in...
295 /* Ok, restore the MMU control register we saved in %g5 */
296 sta %g5, [%g0] ASI_M_MMUREGS ! POW... ouch
460 set sun4d_handler_irq, %g5
462 sub %g5, %g4, %g5
463 srl %g5, 2, %g5
464 or %g5, %g3, %g5
[all …]
H A Dfpu_traps.S7 rdpr %tstate, %g5
8 andcc %g5, %g4, %g0
11 rd %fprs, %g5
12 andcc %g5, FPRS_FEF, %g0
24 ldub [%g6 + TI_FPSAVED], %g5
26 andcc %g5, FPRS_FEF, %g0
30 1: andcc %g5, FPRS_DL, %g0
33 andcc %g5, FPRS_DU, %g0
71 661: ldxa [%g3] ASI_DMMU, %g5
74 ldxa [%g3] ASI_MMU, %g5
[all …]
H A Ddtlb_prot.S21 rdpr %pstate, %g5 ! Move into alt-globals
22 wrpr %g5, PSTATE_AG|PSTATE_MG, %pstate
28 ldxa [%g4] ASI_DMMU, %g5 ! Put tagaccess in %g5
29 srlx %g5, PAGE_SHIFT, %g5
30 sllx %g5, PAGE_SHIFT, %g5 ! Clear context ID bits
H A Dhvtramp.S109 mov 1, %g5
110 sllx %g5, THREAD_SHIFT, %g5
111 sub %g5, (STACKFRAME_SZ + STACK_BIAS), %g5
112 add %g6, %g5, %sp
H A Dspiterrs.S25 ldxa [%g0] ASI_AFAR, %g5 ! Get AFAR
162 mov DMMU_SFAR, %g5
164 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
190 mov DMMU_SFAR, %g5
192 ldxa [%g5] ASI_DMMU, %g5 ! Get SFAR
211 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
230 rdpr %tpc, %g5 ! IMMU has no SFAR, use TPC
H A Ditlb_miss.S5 srlx %g6, 48, %g5 ! Get context
7 brz,pn %g5, kvmap_itlb ! Context 0 processing
16 andcc %g5, %g4, %g0 ! Executable?
19 stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
H A Divec.S5 * [high 32-bits] MMU Context Argument 0, place in %g5
21 srlx %g3, 32, %g5
32 ldx [%g6], %g5
33 stxa %g5, [%g3] ASI_PHYS_USE_EC
H A Dmisctrap.S30 /* Setup %g4/%g5 now as they are used in the
36 ldxa [%g3] ASI_DMMU, %g5
56 ldxa [%g4] ASI_DMMU, %g5
74 ldxa [%g4] ASI_DMMU, %g5
H A Ddtlb_miss.S5 srlx %g6, 48, %g5 ! Get context
7 brz,pn %g5, kvmap_dtlb ! Context 0 processing
15 stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Load TLB
/linux/arch/sparc/mm/
H A Dviking.S54 sll %o2, 26, %g5 ! block << 26
56 or %g5, %g4, %g5
57 ldda [%g5] ASI_M_DATAC_TAG, %g2
81 sll %o2, 26, %g5 ! block << 26
124 WINDOW_FLUSH(%g4, %g5)
137 lda [%g1] ASI_M_MMUREGS, %g5
146 sta %g5, [%g1] ASI_M_MMUREGS
156 lda [%g1] ASI_M_MMUREGS, %g5
171 sta %g5, [%g1] ASI_M_MMUREGS
181 lda [%g1] ASI_M_MMUREGS, %g5
[all …]
H A Dhypersparc.S28 WINDOW_FLUSH(%g4, %g5)
30 ld [%g4 + %lo(vac_cache_size)], %g5
34 subcc %g5, %g2, %g5 ! hyper_flush_unconditional_combined
36 sta %g0, [%g5] ASI_M_FLUSH_CTX
47 WINDOW_FLUSH(%g4, %g5)
57 add %o1, %g4, %g5
58 add %o1, %g5, %o4
70 sta %g0, [%o0 + %g5] ASI_M_FLUSH_USER
85 WINDOW_FLUSH(%g4, %g5)
100 sll %o3, 2, %g5
[all …]
H A Dswift.S43 WINDOW_FLUSH(%g4, %g5)
59 WINDOW_FLUSH(%g4, %g5)
66 lda [%g7] ASI_M_MMUREGS, %g5
99 sta %g5, [%g7] ASI_M_MMUREGS
125 WINDOW_FLUSH(%g4, %g5)
132 lda [%g7] ASI_M_MMUREGS, %g5
165 sta %g5, [%g7] ASI_M_MMUREGS
248 lda [%g1] ASI_M_MMUREGS, %g5
252 sta %g5, [%g1] ASI_M_MMUREGS
H A Dultra.S520 * %g5 mm->context (all tlb flushes)
536 or %g5, %g4, %g5 /* Preserve nucleus page size fields */
537 stxa %g5, [%g2] ASI_DMMU
559 /* %g5=context, %g1=vaddr */
564 or %g5, %g4, %g5
566 stxa %g5, [%g4] ASI_DMMU
569 andn %g1, 0x1, %g5
570 stxa %g0, [%g5] ASI_IMMU_DEMAP
571 2: stxa %g0, [%g5] ASI_DMMU_DEMAP
809 %g5 == (page->mapping != NULL) */
[all …]
/linux/arch/sparc/lib/
H A Dchecksum_32.S117 5: CSUM_BIGCHUNK(%o0, 0x00, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
118 CSUM_BIGCHUNK(%o0, 0x20, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
119 CSUM_BIGCHUNK(%o0, 0x40, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
120 CSUM_BIGCHUNK(%o0, 0x60, %o2, %o4, %o5, %g2, %g3, %g4, %g5)
133 cptbl: CSUM_LASTCHUNK(%o0, 0x68, %o2, %g2, %g3, %g4, %g5)
134 CSUM_LASTCHUNK(%o0, 0x58, %o2, %g2, %g3, %g4, %g5)
135 CSUM_LASTCHUNK(%o0, 0x48, %o2, %g2, %g3, %g4, %g5)
136 CSUM_LASTCHUNK(%o0, 0x38, %o2, %g2, %g3, %g4, %g5)
137 CSUM_LASTCHUNK(%o0, 0x28, %o2, %g2, %g3, %g4, %g5)
138 CSUM_LASTCHUNK(%o0, 0x18, %o2, %g2, %g3, %g4, %g5)
[all …]
H A Dmemcpy.S158 MOVE_BIGCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
159 MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
160 MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
161 MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
182 MOVE_LASTCHUNK(o1, o0, 0x60, g2, g3, g4, g5)
183 MOVE_LASTCHUNK(o1, o0, 0x50, g2, g3, g4, g5)
184 MOVE_LASTCHUNK(o1, o0, 0x40, g2, g3, g4, g5)
185 MOVE_LASTCHUNK(o1, o0, 0x30, g2, g3, g4, g5)
186 MOVE_LASTCHUNK(o1, o0, 0x20, g2, g3, g4, g5)
187 MOVE_LASTCHUNK(o1, o0, 0x10, g2, g3, g4, g5)
[all …]
H A Dcopy_user.S56 mov offset, %g5; \
63 mov offset, %g5; \
95 sub %g7, %g5, %o0
113 sub %g1, %g5, %o0
136 sub %o3, %g5, %o3
151 sub %o2, %g5, %o0
217 MOVE_BIGCHUNK(o1, o0, 0x00, o2, o3, o4, o5, g2, g3, g4, g5)
218 MOVE_BIGCHUNK(o1, o0, 0x20, o2, o3, o4, o5, g2, g3, g4, g5)
219 MOVE_BIGCHUNK(o1, o0, 0x40, o2, o3, o4, o5, g2, g3, g4, g5)
220 MOVE_BIGCHUNK(o1, o0, 0x60, o2, o3, o4, o5, g2, g3, g4, g5)
[all …]
H A Dblockops.S77 MIRROR_BLOCK(%o0, %o1, 0x00, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
78 MIRROR_BLOCK(%o0, %o1, 0x20, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
79 MIRROR_BLOCK(%o0, %o1, 0x40, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
80 MIRROR_BLOCK(%o0, %o1, 0x60, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
81 MIRROR_BLOCK(%o0, %o1, 0x80, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
82 MIRROR_BLOCK(%o0, %o1, 0xa0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
83 MIRROR_BLOCK(%o0, %o1, 0xc0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
84 MIRROR_BLOCK(%o0, %o1, 0xe0, %o2, %o3, %o4, %o5, %g2, %g3, %g4, %g5)
/linux/arch/sparc/include/asm/
H A Dxor_32.h34 "xor %%g5, %%l1, %%g5\n\t" in sparc_2()
45 : "g2", "g3", "g4", "g5", in sparc_2()
74 "xor %%g5, %%l1, %%g5\n\t" in sparc_3()
85 "xor %%g5, %%l1, %%g5\n\t" in sparc_3()
96 : "g2", "g3", "g4", "g5", in sparc_3()
127 "xor %%g5, %%l1, %%g5\n\t" in sparc_4()
139 "xor %%g5, %%l1, %%g5\n\t" in sparc_4()
150 "xor %%g5, %%l1, %%g5\n\t" in sparc_4()
161 : "g2", "g3", "g4", "g5", in sparc_4()
194 "xor %%g5, %%l1, %%g5\n\t" in sparc_5()
[all …]
/linux/drivers/macintosh/
H A DKconfig102 This option adds support for the newer G5 iMacs and PowerMacs based
197 tristate "Support for thermal management on iMac G5"
204 tristate "Support for thermal management on PowerMac G5 (AGP)"
208 This driver provides thermal control for the PowerMac G5
212 tristate "Support for thermal management on Xserve G5"
216 This driver provides thermal control for the Xserve G5
225 which is the recent (SMU based) single CPU desktop G5
233 which are the recent dual and quad G5 machines using the
242 which is the iMac G5 (iSight).

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