| /freebsd/sys/contrib/device-tree/Bindings/fpga/ |
| H A D | fpga-region.yaml | 1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/fpga/fpga-region.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: FPGA Region
10 - Michal Simek <michal.simek@amd.com>
14 - Introduction
15 - Terminology
16 - Sequence
17 - FPGA Region
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| H A D | fpga-region.txt | 1 FPGA Region Device Tree Binding
6 - Introduction
7 - Terminology
8 - Sequence
9 - FPGA Region
10 - Supported Use Models
11 - Device Tree Examples
12 - Constraints
18 FPGA Region
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| H A D | xlnx,versal-fpga.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,versal-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Versal FPGA driver.
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Device Tree Versal FPGA bindings for the Versal SoC, controlled
19 - enum:
20 - xlnx,versal-fpga
23 - compatible
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| H A D | xlnx,fpga-selectmap.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-selectmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx SelectMAP FPGA interface
10 - Charles Perry <charles.perry@savoirfairelinux.com>
22 - $ref: /schemas/memory-controllers/mc-peripheral-props.yaml#
27 - xlnx,fpga-xc7s-selectmap
28 - xlnx,fpga-xc7a-selectmap
29 - xlnx,fpga-xc7k-selectmap
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| H A D | xlnx,zynqmp-pcap-fpga.yaml | 1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,zynqmp-pcap-fpga.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Zynq Ultrascale MPSoC FPGA Manager
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Device Tree Bindings for Zynq Ultrascale MPSoC FPGA Manager.
20 const: xlnx,zynqmp-pcap-fpga
23 - compatible
28 - |
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| H A D | lattice,sysconfig.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/lattice,sysconfig.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Lattice Slave SPI sysCONFIG FPGA manager
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Lattice sysCONFIG port, which is used for FPGA configuration, among others,
18 format into FPGA's SRAM configuration memory.
23 - lattice,sysconfig-ecp5
28 program-gpios:
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| H A D | microchip,mpf-spi-fpga-mgr.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/microchip,mpf-spi-fpga-mgr.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Microchip Polarfire FPGA manager.
10 - Vladimir Georgiev <v.georgiev@metrotek.ru>
13 Device Tree Bindings for Microchip Polarfire FPGA Manager using slave SPI to
19 - microchip,mpf-spi-fpga-mgr
26 - compatible
27 - reg
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| H A D | xlnx,fpga-slave-serial.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/fpga/xlnx,fpga-slave-serial.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Xilinx Slave Serial SPI FPGA
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
13 Xilinx Spartan-6 and 7 Series FPGAs support a method of loading the bitstream
21 https://www.xilinx.com/support/documentation/application_notes/xapp583-fpga-configuration.pdf
24 - $ref: /schemas/spi/spi-peripheral-props.yaml#
29 - xlnx,fpga-slave-serial
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| H A D | xlnx,pr-decoupler.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
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| /freebsd/sys/dev/mlx5/mlx5_fpga/ |
| H A D | sdk.h | 1 /*-
6 * General Public License (GPL) Version 2, available from the file
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
39 /* #include <linux/dma-direction.h> */
46 * This header defines the in-kernel API for Innova FPGA client drivers.
55 * struct mlx5_fpga_client - Describes an Innova client driver
62 * @fdev: The FPGA device
67 * @fdev: The FPGA device
70 * Any SBU-specific initialization should happen at this stage
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| H A D | core.h | 1 /*-
6 * General Public License (GPL) Version 2, available from the file
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
41 /* Represents client-specific and Innova device-specific information */
52 MLX5_FDEV_STATE_IN_PROGRESS = 2,
85 dev_dbg(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
86 __func__, __LINE__, current->pid, ##__VA_ARGS__)
89 dev_err(&(__adev)->mdev->pdev->dev, "FPGA: %s:%d:(pid %d): " format, \
90 __func__, __LINE__, current->pid, ##__VA_ARGS__)
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| H A D | mlx5fpga_ipsec.c | 1 /*-
6 * General Public License (GPL) Version 2, available from the file
14 * - Redistributions of source code must retain the above
18 * - Redistributions in binary form must reproduce the above
45 MLX5_IPSEC_RESPONSE_SADB_ISSUE = 2,
80 if (!mdev->fpga || !MLX5_CAP_GEN(mdev, fpga)) in mlx5_fpga_is_ipsec_device()
106 context->status = MLX5_FPGA_IPSEC_SACMD_SEND_FAIL; in mlx5_fpga_ipsec_send_complete()
107 complete(&context->complete); in mlx5_fpga_ipsec_send_complete()
117 return -EEXIST; in syndrome_to_errno()
119 return -EINVAL; in syndrome_to_errno()
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| /freebsd/sys/contrib/device-tree/Bindings/board/ |
| H A D | fsl,fpga-qixis.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA/CPLD
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - const: fsl,p1022ds-fpga
17 - const: fsl,fpga-ngpixis
18 - items:
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| H A D | fsl,fpga-qixis-i2c.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/board/fsl,fpga-qixis-i2c.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale on-board FPGA connected on I2C bus
10 - Frank Li <Frank.Li@nxp.com>
15 - items:
16 - enum:
17 - fsl,bsc9132qds-fpga
18 - const: fsl,fpga-qixis-i2c
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| /freebsd/sys/contrib/device-tree/src/powerpc/fsl/ |
| H A D | gef_ppc9a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_ppc9a.dtb gef_ppc9a.dts
17 /include/ "mpc8641si-pre.dtsi"
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,ppc9a-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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| H A D | gef_sbc310.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc310.dtb gef_sbc310.dts
17 /include/ "mpc8641si-pre.dtsi"
33 2 0 0xe8000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00010000>; // FPGA
39 compatible = "gef,sbc310-firmware-mirror", "cfi-flash";
41 bank-width = <2>;
42 device-width = <2>;
43 #address-cells = <1>;
44 #size-cells = <1>;
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| H A D | gef_sbc610.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
14 * Compiled with dtc -I dts -O dtb -o gef_sbc610.dtb gef_sbc610.dts
17 /include/ "mpc8641si-pre.dtsi"
33 2 0 0xe0000000 0x08000000 // Paged Flash 1
35 4 0 0xfc000000 0x00008000 // FPGA
36 5 0 0xfc008000 0x00008000 // AFIX FPGA
37 6 0 0xfd000000 0x00800000 // IO FPGA (8-bit)
38 7 0 0xfd800000 0x00800000>; // IO FPGA (32-bit)
42 compatible = "gef,sbc610-firmware-mirror", "cfi-flash";
44 bank-width = <4>;
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| H A D | ge_imp3a.dts | 1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Copyright 2010-2011 GE Intelligent Platforms Embedded Systems, Inc.
11 /include/ "p2020si-pre.dtsi"
35 #address-cells = <1>;
36 #size-cells = <1>;
37 compatible = "ge,imp3a-firmware-mirror", "cfi-flash";
39 bank-width = <2>;
40 device-width = <1>;
45 read-only;
51 #address-cells = <1>;
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| /freebsd/sys/contrib/device-tree/Bindings/bus/ |
| H A D | ts-nbus.txt | 4 Systems FPGA on the TS-4600 SoM.
7 - compatible : "technologic,ts-nbus"
8 - #address-cells : must be 1
9 - #size-cells : must be 0
10 - pwms : The PWM bound to the FPGA
11 - ts,data-gpios : The 8 GPIO pins connected to the data lines on the FPGA
12 - ts,csn-gpios : The GPIO pin connected to the csn line on the FPGA
13 - ts,txrx-gpios : The GPIO pin connected to the txrx line on the FPGA
14 - ts,strobe-gpios : The GPIO pin connected to the stobe line on the FPGA
15 - ts,ale-gpios : The GPIO pin connected to the ale line on the FPGA
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | mdio-mux-mmioreg.txt | 1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
4 like an FPGA, is used to control which child bus is connected. The mdio-mux
5 node must be a child of the memory-mapped device. The driver currently only
6 supports devices with 8, 16 or 32-bit registers.
10 - compatible : string, must contain "mdio-mux-mmioreg"
12 - reg : integer, contains the offset of the register that controls the bus
14 register, and must therefore be 1, 2, or 4.
16 - mux-mask : integer, contains an eight-bit mask that specifies which
18 'reg' property of each child mdio-mux node must be constrained by
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| /freebsd/sys/contrib/device-tree/Bindings/firmware/xilinx/ |
| H A D | xlnx,zynqmp-firmware.yaml | 1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/firmware/xilinx/xlnx,zynqmp-firmware.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Nava kishore Manne <nava.kishore.manne@amd.com>
12 description: The zynqmp-firmware node describes the interface to platform
17 power management service, FPGA service and other platform management
23 - description: For implementations complying for Zynq Ultrascale+ MPSoC.
24 const: xlnx,zynqmp-firmware
26 - description: For implementations complying for Versal.
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| /freebsd/sys/contrib/device-tree/Bindings/pinctrl/ |
| H A D | cirrus,lochnagar.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - patches@opensource.cirrus.com
15 Logic devices on mini-cards, as well as allowing connection of various
26 [2] Pinctrl: ../pinctrl/pinctrl-bindings.txt
29 [3] include/dt-bindings/pinctrl/lochnagar.h
37 - cirrus,lochnagar-pinctrl
39 gpio-controller: true
41 '#gpio-cells':
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| /freebsd/sys/contrib/device-tree/Bindings/gpio/ |
| H A D | gpio-ts4900.txt | 1 * Technologic Systems I2C-FPGA's GPIO controller bindings
3 This bindings describes the GPIO controller for Technologic's FPGA core.
4 TS-4900's FPGA encodes the GPIO state on 3 bits, whereas the TS-7970's FPGA
5 uses 2 bits: it doesn't use a dedicated input bit.
8 - compatible: Should be one of the following
9 "technologic,ts4900-gpio"
10 "technologic,ts7970-gpio"
11 - reg: Physical base address of the controller and length
13 - #gpio-cells: Should be two. The first cell is the pin number.
14 - gpio-controller: Marks the device node as a gpio controller.
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| /freebsd/sys/contrib/device-tree/Bindings/ |
| H A D | xilinx.txt | 7 implemented within the fpga fabric every instance of the device can be
10 Each IP-core has a set of parameters which the FPGA designer can use to
15 to be recompiled every time the FPGA bitstream is resynthesized.
18 generate a new device tree each time the FPGA bitstream changes. The
20 properties of the device node. In general, device nodes for IP-cores
23 (name): (generic-name)@(base-address) {
24 compatible = "xlnx,(ip-core-name)-(HW_VER)"
27 interrupt-parent = <&interrupt-controller-phandle>;
29 xlnx,(parameter1) = "(string-value)";
30 xlnx,(parameter2) = <(int-value)>;
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| /freebsd/sys/dev/sfxge/common/ |
| H A D | efx_regs_mcdi_strs.h | 1 /*-
2 * SPDX-License-Identifier: BSD-2-Clause
4 * Copyright 2008-2018 Solarflare Communications Inc. All rights reserved.
11 * 2. Redistributions in binary form must reproduce the above copyright
31 * rebuild this file with "make -C doc mcdiheaders".
54 #define MC_CMD_SENSOR_OUT_VAOE_ENUM_STR "AOE FPGA power: mV"
55 #define MC_CMD_SENSOR_AOE_TEMP_ENUM_STR "AOE FPGA temperature: degC"
56 #define MC_CMD_SENSOR_PSU_AOE_TEMP_ENUM_STR "AOE FPGA PSU temperature: degC"
60 #define MC_CMD_SENSOR_FAN_2_ENUM_STR "Fan 2 speed: RPM"
63 #define MC_CMD_SENSOR_IN_VAOE_ENUM_STR "AOE FPGA input power: mV"
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