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/linux/arch/arm/kernel/
H A Dfiq.c3 * linux/arch/arm/kernel/fiq.c
8 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
10 * FIQ support re-written by Russell King to be more generic
12 * We now properly support a method by which the FIQ handlers can
14 * the FIQ vector itself.
17 * 1. Owner A claims FIQ:
22 * - enables FIQ.
23 * 3. Owner B claims FIQ:
31 * - enables FIQ.
32 * 5. Owner B releases FIQ:
[all …]
H A Dfiqasm.S4 * Derived from code originally in linux/arch/arm/kernel/fiq.c:
10 * FIQ support written by Philip Blundell <philb@gnu.org>, 1998.
12 * FIQ support re-written by Russell King to be more generic
21 * Taking an interrupt in FIQ mode is death, so both these functions
28 msr cpsr_c, r2 @ select FIQ mode
41 msr cpsr_c, r2 @ select FIQ mode
/linux/fs/fuse/
H A Ddev.c62 * - check the fiq pending list
78 struct fuse_iqueue *fiq = &fc->iq; in fuse_check_timeout() local
86 spin_lock(&fiq->lock); in fuse_check_timeout()
87 expired = fuse_request_expired(fc, &fiq->pending); in fuse_check_timeout()
88 spin_unlock(&fiq->lock); in fuse_check_timeout()
303 static u64 fuse_get_unique_locked(struct fuse_iqueue *fiq) in fuse_get_unique_locked() argument
305 fiq->reqctr += FUSE_REQ_ID_STEP; in fuse_get_unique_locked()
306 return fiq->reqctr; in fuse_get_unique_locked()
309 u64 fuse_get_unique(struct fuse_iqueue *fiq) in fuse_get_unique() argument
313 spin_lock(&fiq->lock); in fuse_get_unique()
[all …]
/linux/arch/arm/mach-omap1/
H A Dams-delta-fiq.c3 * Amstrad E3 FIQ handling
20 #include <linux/platform_data/ams-delta-fiq.h>
23 #include <asm/fiq.h>
27 #include "ams-delta-fiq.h"
31 .name = "ams-delta-fiq"
35 * This buffer is shared between FIQ and IRQ contexts.
36 * The FIQ and IRQ isrs can both read and write it.
38 * followed by the circular buffer where the FIQ isr stores
40 * <linux/platform_data/ams-delta-fiq.h> for details of offsets.
60 * until the IRQ counter catches the FIQ incremented interrupt counter. in deferred_fiq()
[all …]
H A Dams-delta-fiq-handler.S3 * linux/arch/arm/mach-omap1/ams-delta-fiq-handler.S
14 #include <linux/platform_data/ams-delta-fiq.h>
22 #include "ams-delta-fiq.h"
93 @ FIQ intrrupt handler
100 beq .Lexit @ none - spurious FIQ? exit
104 mov r8, #2 @ reset FIQ agreement
114 subs pc, lr, #4 @ return from FIQ
138 @ Keyboard clock FIQ mode interrupt handler
222 @ Hook switch interrupt FIQ mode simple handler
239 @ Modem FIQ mode interrupt handler stub
[all …]
H A Dirq.c97 * NOTE: There is currently no OMAP fiq handler for Linux. Read the
98 * mailing list threads on FIQ handlers if you are planning to
99 * add a FIQ handler for OMAP.
101 static void omap_irq_set_cfg(int irq, int fiq, int priority, int trigger) in omap_irq_set_cfg() argument
107 /* FIQ is only available on bank 0 interrupts */ in omap_irq_set_cfg()
108 fiq = bank ? 0 : (fiq & 0x1); in omap_irq_set_cfg()
109 val = fiq | ((priority & 0x1f) << 2) | ((trigger & 0x1) << 1); in omap_irq_set_cfg()
H A Dams-delta-fiq.h4 * arch/arm/mach-omap1/ams-delta-fiq.h
6 * Taken from the original Amstrad modifications to fiq.h
22 * Interrupt number used for passing control from FIQ to IRQ.
/linux/arch/arm/include/asm/
H A Dfiq.h3 * arch/arm/include/asm/fiq.h
5 * Support for FIQ on ARM architectures.
9 * NOTE: The FIQ mode registers are not magically preserved across
28 * reacquire FIQ
40 extern void enable_fiq(int fiq);
41 extern void disable_fiq(int fiq);
/linux/Documentation/devicetree/bindings/interrupt-controller/
H A Dapple,aic.yaml31 This device also represents the FIQ interrupt sources on platforms using AIC,
62 - 1: FIQ
89 FIQ affinity can be expressed as a single "affinities" node,
90 containing a set of sub-nodes, one per FIQ with a non-default
97 apple,fiq-index:
99 The interrupt number specified as a FIQ, and for which
110 - apple,fiq-index
H A Dcirrus,ep7209-intc.yaml18 1: BLINT Battery low (FIQ)
19 3: MCINT Media changed (FIQ)
37 32: DAIINT DAI interface (FIQ)
H A Dst,stih407-irq-syscfg.yaml32 st,fiq-device:
50 - st,fiq-device
62 st,fiq-device = <ST_IRQ_SYSCFG_DISABLED>,
/linux/drivers/irqchip/
H A Dirq-apple-aic.c36 * - FIQ hwirq numbers are assigned after true hwirqs, and are per-cpu.
39 * - <1 nr flags> - FIQ #nr
163 * IMP-DEF sysregs that control FIQ sources
182 /* Guest timer FIQ enable register */
216 * FIQ hwirq index definitions: FIQ sources use the DT binding defines
475 * FIQ irqchip
544 * the FIQ source state without having to peek down into sources... in aic_handle_fiq()
553 * Since not dealing with any of these results in a FIQ storm, in aic_handle_fiq()
592 pr_err_ratelimited("Uncore PMC FIQ fired. Masking.\n"); in aic_handle_fiq()
604 .name = "AIC-FIQ",
[all …]
H A Dirq-ixp4xx.c28 #define IXP4XX_ICLR 0x08 /* Interrupt IRQ/FIQ Select */
30 #define IXP4XX_ICFP 0x10 /* FIQ Status */
33 #define IXP4XX_ICFH 0x1C /* FIQ Highest Pri Int */
38 #define IXP4XX_ICLR2 0x28 /* Interrupt IRQ/FIQ Select 2 */
40 #define IXP4XX_ICFP2 0x30 /* FIQ Status */
214 /* Route all sources to IRQ instead of FIQ */ in ixp4xx_irq_setup()
221 /* Route upper 32 sources to IRQ instead of FIQ */ in ixp4xx_irq_setup()
H A Dirq-st.c89 /* Select IRQ/FIQ channel for device. */ in st_irq_xlate()
110 channels = of_property_count_u32_elems(np, "st,fiq-device"); in st_irq_syscfg_enable()
112 dev_err(&pdev->dev, "st,enable-fiq-device must have 2 elems\n"); in st_irq_syscfg_enable()
123 of_property_read_u32_index(np, "st,fiq-device", i, &device); in st_irq_syscfg_enable()
/linux/arch/arm64/mm/
H A Dtrans_pgd-asm.S43 invalid_vector hyp_stub_el2t_fiq_invalid // FIQ EL2t
48 invalid_vector hyp_stub_el2h_fiq_invalid // FIQ EL2h
53 invalid_vector hyp_stub_el1_fiq_invalid // FIQ 64-bit EL1
58 invalid_vector hyp_stub_32b_el1_fiq_invalid // FIQ 32-bit EL1
/linux/include/linux/irqchip/
H A Dirq-bcm2836.h13 * next 2 bits identify the CPU that the GPU FIQ goes to.
22 * next 4 bits are the CPU's timer FIQ enables (which override the IRQ
28 * the next 4 bits are the CPU's per-mailbox FIQ enables (which
37 /* Same status bits as above, but for FIQ. */
/linux/arch/arm64/kernel/
H A Dentry.S522 kernel_ventry 1, t, 64, fiq // FIQ EL1t
527 kernel_ventry 1, h, 64, fiq // FIQ EL1h
532 kernel_ventry 0, t, 64, fiq // FIQ 64-bit EL0
537 kernel_ventry 0, t, 32, fiq // FIQ 32-bit EL0
588 entry_handler 1, t, 64, fiq
593 entry_handler 1, h, 64, fiq
598 entry_handler 0, t, 64, fiq
603 entry_handler 0, t, 32, fiq
786 kernel_ventry 1, t, 64, fiq // FIQ EL1h
791 kernel_ventry 1, h, 64, fiq // FIQ EL1h
H A Dhyp-stub.S27 ventry el2_fiq_invalid // FIQ EL2t
32 ventry el2_fiq_invalid // FIQ EL2h
37 ventry el1_fiq_invalid // FIQ 64-bit EL1
42 ventry el1_fiq_invalid // FIQ 32-bit EL1
/linux/arch/arm/mach-rpc/
H A Ddma.c17 #include <asm/fiq.h>
262 unsigned int fiq; member
290 printk("floppydma: couldn't claim FIQ.\n"); in floppy_enable_dma()
296 enable_fiq(fdma->fiq); in floppy_enable_dma()
302 disable_fiq(fdma->fiq); in floppy_disable_dma()
339 .fiq = FIQ_FLOPPYDATA,
/linux/arch/arm64/kvm/hyp/
H A Dhyp-entry.S184 invalid_vect el2t_fiq_invalid // FIQ EL2t
189 invalid_vect el2h_fiq_invalid // FIQ EL2h
194 valid_vect el1_fiq // FIQ 64-bit EL1
199 valid_vect el1_fiq // FIQ 32-bit EL1
/linux/arch/arm64/kvm/hyp/nvhe/
H A Dhyp-init.S29 ventry . // FIQ EL2t
34 ventry . // FIQ EL2h
39 ventry . // FIQ 64-bit EL1
44 ventry . // FIQ 32-bit EL1
/linux/arch/arm/mach-imx/
H A Dssi-fiq.S37 * mark the function body so that it can be copied to the FIQ vector in
39 * of an FIQ: calling it directly will not work.
129 @ return from FIQ
/linux/arch/arm64/include/asm/
H A Dirqflags.h14 * FIQ exceptions, in the 'daif' register. We mask and unmask them in 'daif'
17 * Masking SError masks IRQ/FIQ, but not debug exceptions. IRQ and FIQ are
/linux/tools/perf/pmu-events/arch/arm64/fujitsu/monaka/
H A Dexception.json32 …"BriefDescription": "This event counts only FIQ exceptions that are taken locally, including Virtu…
/linux/include/linux/platform_data/
H A Dams-delta-fiq.h4 * include/linux/platform_data/ams-delta-fiq.h
6 * Taken from the original Amstrad modifications to fiq.h

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