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/linux/tools/perf/pmu-events/arch/x86/knightslanding/
H A Dcache.json3 …the L2Q because of any L2 queue reject condition. There is no concept of at-ret here. It might in…
42 … and L1 evictions (automatically excludes L2HWP, UC, WC) that were rejected - Multiple repeated re…
49 "BriefDescription": "Counts all the load micro-ops retired",
53 "PublicDescription": "This event counts the number of load micro-ops retired.",
58 "BriefDescription": "Counts all the store micro-ops retired",
62 "PublicDescription": "This event counts the number of store micro-ops retired.",
67 …ounts the loads retired that get the data from the other core in the same tile in M state (Precise…
73 …"PublicDescription": "This event counts the number of load micro-ops retired that got data from an…
78 "BriefDescription": "Counts the number of load micro-ops retired that miss in L1 D cache",
82 …"PublicDescription": "This event counts the number of load micro-ops retired that miss in L1 Data …
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/linux/arch/arm/mach-versatile/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0
52 bool "Include support for Integrator/IM-PD1"
60 The IM-PD1 is an add-on logic module for the Integrator which
62 The IM-PD1 can be found on the Integrator/PP2 platform.
77 bool "Integrator/CM922T-XA10 core module"
83 bool "Integrator/CM926EJ-S core module"
107 bool "Integrator/CM1026EJ-S core module"
113 bool "Integrator/CM1136JF-S core module"
129 bool "Integrator/CT926 (ARM926EJ-S) core tile"
135 bool "Integrator/CTB36 (ARM1136JF-S) core tile"
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/linux/drivers/gpu/drm/sun4i/
H A Dsun4i_frontend.h1 // SPDX-License-Identifier: GPL-2.0+
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
42 * end line of the current tile and the start of the first line in the next
43 * vertical tile.
45 * Tiles are represented in row-major order, thus the end line of current tile
46 * starts at: 31 * 32 (31 lines of 32 cols), the next vertical tile starts at:
47 * 32-bit-aligned-width * 32 and the distance is:
48 * 32 * (32-bit-aligned-width - 31).
50 #define SUN4I_FRONTEND_LINESTRD_TILED(stride) (((stride) - 31) * 32)
79 #define SUN4I_FRONTEND_INSIZE(h, w) ((((h) - 1) << 16) | (((w) - 1)))
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/linux/drivers/media/platform/mediatek/vcodec/decoder/vdec/
H A Dvdec_av1_req_lat_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
22 #define AV1_REF_INVALID_SCALE -1
26 #define AV1_INVALID_IDX -1
39 (((_value_) < 0) ? -AV1_DIV_ROUND_UP_POW2(-(_value_), (_n_)) \
43 #define BIT_FLAG(x, bit) (!!((x)->flags & (bit)))
44 #define SEGMENTATION_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEGMENTATION_FLAG_##name))
45 #define QUANT_FLAG(x, name) (!!((x)->flags & V4L2_AV1_QUANTIZATION_FLAG_##name))
46 #define SEQUENCE_FLAG(x, name) (!!((x)->flags & V4L2_AV1_SEQUENCE_FLAG_##name))
47 #define FH_FLAG(x, name) (!!((x)->flags & V4L2_AV1_FRAME_FLAG_##name))
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H A Dvdec_vp9_req_lat_if.c1 // SPDX-License-Identifier: GPL-2.0
9 #include <media/videobuf2-dma-contig.h>
10 #include <media/v4l2-vp9.h>
28 #define HDR_FLAG(x) (!!((hdr)->flags & V4L2_VP9_FRAME_FLAG_##x))
29 #define LF_FLAG(x) (!!((lf)->flags & V4L2_VP9_LOOP_FILTER_FLAG_##x))
30 #define SEG_FLAG(x) (!!((seg)->flags & V4L2_VP9_SEGMENTATION_FLAG_##x))
34 * struct vdec_vp9_slice_frame_ctx - vp9 prob tables footprint
85 * struct vdec_vp9_slice_frame_counts - vp9 counts tables footprint
139 * struct vdec_vp9_slice_counts_map - vp9 counts tables to map
168 * struct vdec_vp9_slice_uncompressed_header - vp9 uncompressed header syntax
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/linux/arch/arm/boot/dts/arm/
H A Darm-realview-eb-11mp.dts23 /dts-v1/;
24 #include "arm-realview-eb-mp.dtsi"
27 model = "ARM RealView Emulation Baseboard with ARM11MPCore Rev C Core Tile";
31 * This is the ARM11 MPCore tile (HBI-0146) used with the RealView EB.
32 * Reference: ARM DUI 0318F
35 * qemu-system-arm -M realview-eb-mpcore -smp cpus=4
38 #address-cells = <1>;
39 #size-cells = <0>;
40 enable-method = "arm,realview-smp";
46 next-level-cache = <&L2>;
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/linux/drivers/gpu/drm/exynos/
H A Dexynos_drm_scaler.c1 // SPDX-License-Identifier: GPL-2.0-only
25 #include "regs-scaler.h"
27 #define scaler_read(offset) readl(scaler->regs + (offset))
28 #define scaler_write(cfg, offset) writel(cfg, scaler->regs + (offset))
100 } while (--retry > 1 && in scaler_reset()
105 } while (--retry > 0 && scaler_read(SCALER_INT_EN) != 1); in scaler_reset()
107 return retry ? 0 : -EIO; in scaler_reset()
144 u32 src_fmt, u32 tile) in scaler_set_src_fmt() argument
148 val = SCALER_SRC_CFG_SET_COLOR_FORMAT(src_fmt) | (tile << 10); in scaler_set_src_fmt()
162 for (i = 0; i < src_buf->format->num_planes; ++i) in scaler_set_src_base()
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/linux/drivers/gpu/drm/msm/disp/dpu1/
H A Dmsm_media_info.h5 #define MSM_MEDIA_ALIGN(__sz, __align) (((__align) & ((__align) - 1)) ?\
6 ((((__sz) + (__align) - 1) / (__align)) * (__align)) :\
7 (((__sz) + (__align) - 1) & (~((__align) - 1))))
11 #define MSM_MEDIA_ROUNDUP(__sz, __r) (((__sz) + ((__r) - 1)) / (__r))
24 * <-------- Y/UV_Stride -------->
25 * <------- Width ------->
44 * . . . . . . . . . . . . . . . . --> Buffer size alignment
50 * Extradata: Arbitrary (software-imposed) padding
62 * <-------- Y/UV_Stride -------->
63 * <------- Width ------->
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/linux/include/linux/
H A Dfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
7 #define FBIO_CURSOR _IOWR('F', 0x08, struct fb_cursor_user)
77 __u32 serial; /* Serial Number - Integer */
84 __u16 input; /* display type - see FB_DISP_* */
85 __u16 dpms; /* DPMS support - see FB_DPMS_ */
86 __u16 signal; /* Signal Type - see FB_SIGNAL_* */
89 __u16 gamma; /* Gamma - in fractions of 100 */
91 __u16 misc; /* Misc flags - see FB_MISC_* */
133 /* only used by mach-pxa/am200epd.c */
197 /* Format: test_bit(width - 1, blit_x) */
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/linux/drivers/gpu/drm/nouveau/
H A Dnouveau_drv.h1 /* SPDX-License-Identifier: MIT */
17 * - added support for tiled system memory buffer objects
18 * - added support for NOUVEAU_GETPARAM_GRAPH_UNITS on [nvc0,nve0].
19 * - added support for compressed memory storage types on [nvc0,nve0].
20 * - added support for software methods 0x600,0x644,0x6ac on nvc0
25 * - fixes multiple bugs in flip completion events and timestamping
27 * - object api exposed to userspace
28 * - fermi,kepler,maxwell zbc
30 * - allow concurrent access to bo's mapped read/write.
32 * - add NOUVEAU_GEM_DOMAIN_COHERENT flag
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/linux/drivers/media/platform/mediatek/mdp3/
H A Dmtk-mdp3-regs.h1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
11 #include <media/videobuf2-core.h>
12 #include "mtk-img-ipi.h"
17 * H-subsample: 0, 1, 2
18 * V-subsample: 0, 1
19 * Color group: 0-RGB, 1-YUV, 2-raw
107 /* For bayer+mono raw-16 */
159 /* Packed 10-bit formats */
162 /* Packed 10-bit UYVY */
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/linux/drivers/gpu/drm/amd/display/dc/dml/
H A Ddml1_display_rq_dlg_calc.c33 * This file is gcc-parseable HW gospel, coming straight from HW engineers.
37 * remain as-is as it provides us with a guarantee from HW that it is correct.
117 DTRACE("DLG: %s: refclk_freq_in_mhz = %3.2f", __func__, refclk_freq_in_mhz); in get_refcyc_per_delivery()
118 DTRACE("DLG: %s: pclk_freq_in_mhz = %3.2f", __func__, pclk_freq_in_mhz); in get_refcyc_per_delivery()
120 DTRACE("DLG: %s: vratio = %3.2f", __func__, vratio); in get_refcyc_per_delivery()
122 DTRACE("DLG: %s: refcyc_per_delivery= %3.2f", __func__, refcyc_per_delivery); in get_refcyc_per_delivery()
142 double tmp0 = (max_num_sw * swath_height) / (l_sw - (prefill - 3.0) / 2.0); in get_vratio_pre()
151 DTRACE("DLG: %s: vinit = %3.2f", __func__, vinit); in get_vratio_pre()
152 DTRACE("DLG: %s: vratio_pre = %3.2f", __func__, vratio_pre); in get_vratio_pre()
155 DTRACE("WARNING_DLG: %s: vratio_pre=%3.2f < 1.0, set to 1.0", __func__, vratio_pre); in get_vratio_pre()
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/linux/include/uapi/drm/
H A Dradeon_drm.h1 /* radeon_drm.h -- Public header for the radeon driver -*- linux-c -*-
66 #define RADEON_UPLOAD_CLIPRECTS 0x00008000 /* handled client-side */
72 /* New style per-packet identifiers for use in cmd_buffer ioctl with
183 #define RADEON_CMD_WAIT 8 /* emit hw wait commands -- note:
234 /* these two defines are DOING IT WRONG - however
332 * a 1K-byte boundary.
336 #define RADEON_OFFSET_MASK (RADEON_OFFSET_ALIGN - 1)
450 /* Counters for client-side throttling of rendering clients.
612 float f[5]; member
640 /* v1.2 - obsoletes drm_radeon_vertex and drm_radeon_indices
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/linux/drivers/gpu/drm/amd/amdgpu/
H A Damdgpu_display.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
52 * amdgpu_display_hotplug_work_func - work handler for display hotplug event
72 struct drm_mode_config *mode_config = &dev->mode_config; in amdgpu_display_hotplug_work_func()
76 mutex_lock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
81 mutex_unlock(&mode_config->mutex); in amdgpu_display_hotplug_work_func()
91 static void amdgpu_display_flip_callback(struct dma_fence *f, in amdgpu_display_flip_callback() argument
97 dma_fence_put(f); in amdgpu_display_flip_callback()
98 schedule_work(&work->flip_work.work); in amdgpu_display_flip_callback()
102 struct dma_fence **f) in amdgpu_display_flip_handle_fence() argument
104 struct dma_fence *fence = *f; in amdgpu_display_flip_handle_fence()
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/linux/include/video/
H A Dsstfb.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * linux/drivers/video/sstfb.h -- voodoo graphics frame buffer
105 # define LFB_WORD_SWIZZLE_WR BIT(11) /* enable write-wordswap (big-endian) */
106 # define LFB_BYTE_SWIZZLE_WR BIT(12) /* enable write-byteswap (big-endian) */
108 # define LFB_WORD_SWIZZLE_RD BIT(15) /* enable read-wordswap (big-endian) */
109 # define LFB_BYTE_SWIZZLE_RD BIT(16) /* enable read-byteswap (big-endian) */
150 # define VIDEO_OFFSET_SHIFT 11 /* unit: #rows tile 64x16/2 */
192 # define BLT_SCR2SCR_BITBLT 0 /* Screen-to-Screen BitBLT */
193 # define BLT_CPU2SCR_BITBLT 1 /* CPU-to-screen BitBLT */
195 # define BLT_16BPP_FMT 2 /* 16 BPP (5-6-5 RGB) */
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/linux/drivers/pci/controller/
H A Dpcie-altera.c1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright Altera Corporation (C) 2013-2015. All rights reserved
46 (((pcie)->hip_base) + (reg) + (1 << 20))
63 (((PCI_DEVID(pcie->root_bus_nr, RP_DEVFN)) << 16) | (tag << 8) | (be))
81 #define AGLX_RP_CFG_ADDR(pcie, reg) (((pcie)->hip_base) + (reg))
151 writel_relaxed(value, pcie->cra_base + reg); in cra_writel()
156 return readl_relaxed(pcie->cra_base + reg); in cra_readl()
162 writew_relaxed(value, pcie->cra_base + reg); in cra_writew()
167 return readw_relaxed(pcie->cra_base + reg); in cra_readw()
173 writeb_relaxed(value, pcie->cra_base + reg); in cra_writeb()
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/linux/scripts/kconfig/lxdialog/
H A Dutil.c1 // SPDX-License-Identifier: GPL-2.0+
38 #define DLG_COLOR(dialog, f, b, h) \ argument
40 dlg.dialog.fg = (f); \
148 init_pair(pair, color->fg, color->bg); in init_one_color()
149 if (color->hl) in init_one_color()
150 color->atr = A_BOLD | COLOR_PAIR(pair); in init_one_color()
152 color->atr = COLOR_PAIR(pair); in init_one_color()
223 /* Display background title if it exists ... - SLH */ in dialog_clear()
231 for (pos = dlg.subtitles; pos != NULL; pos = pos->next) { in dialog_clear()
233 len += strlen(pos->text) + 3; in dialog_clear()
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/linux/drivers/media/platform/raspberrypi/pisp_be/
H A Dpisp_be.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2021-2024 Raspberry Pi Limited.
17 #include <media/v4l2-device.h>
18 #include <media/v4l2-ioctl.h>
19 #include <media/videobuf2-dma-contig.h>
20 #include <media/videobuf2-vmalloc.h>
31 /* Some ISP-BE registers */
83 .ent_name = PISPBE_NAME "-input",
89 .ent_name = PISPBE_NAME "-tdn_input",
95 .ent_name = PISPBE_NAME "-stitch_input",
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/linux/arch/x86/kvm/
H A Dcpuid.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Kernel-based Virtual Machine driver for Linux
55 cpuid_count(0xD, i, &xs->eax, &xs->ebx, &xs->ecx, &ign); in kvm_init_xstate_sizes()
74 offset = (xs->ecx & 0x2) ? ALIGN(ret, 64) : ret; in xstate_required_size()
76 offset = xs->ebx; in xstate_required_size()
77 ret = max(ret, offset + xs->eax); in xstate_required_size()
91 * KVM has a semi-arbitrary rule that querying the guest's CPUID model in kvm_find_cpuid_entry2()
95 * path, e.g. the core VM-Enter/VM-Exit run loop. Nothing will break in kvm_find_cpuid_entry2()
105 if (e->function != function) in kvm_find_cpuid_entry2()
113 if (!(e->flags & KVM_CPUID_FLAG_SIGNIFCANT_INDEX) || e->index == index) in kvm_find_cpuid_entry2()
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/linux/tools/perf/scripts/python/
H A Dexported-sql-viewer.py2 # SPDX-License-Identifier: GPL-2.0
3 # exported-sql-viewer.py: view data from sql database
4 # Copyright (c) 2014-2018, Intel Corporation.
7 # export-to-sqlite.py or the export-to-postgresql.py script. Refer to those
11 # call-graph can be displayed for the pt_example database like this:
13 # python tools/perf/scripts/python/exported-sql-viewer.py pt_example
18 # python tools/perf/scripts/python/exported-sql-viewer.py "hostname=myhost username=myuser password…
20 # The result is a GUI window with a tree representing a context-sensitive
21 # call-graph. Expanding a couple of levels of the tree and adjusting column
26 # v- ls
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/linux/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
52 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/linux/tools/arch/x86/include/asm/
H A Dcpufeatures.h1 /* SPDX-License-Identifier: GPL-2.0 */
8 #define NCAPINTS 22 /* N 32-bit words worth of info */
9 #define NBUGINTS 2 /* N 32-bit bug flags */
17 * please update the table in kernel/cpu/cpuid-deps.c as well.
20 /* Intel-defined CPU features, CPUID level 0x00000001 (EDX), word 0 */
26 #define X86_FEATURE_MSR ( 0*32+ 5) /* "msr" Model-Specific Registers */
37 #define X86_FEATURE_PSE36 ( 0*32+17) /* "pse36" 36-bit PSEs */
47 #define X86_FEATURE_HT ( 0*32+28) /* "ht" Hyper-Threading */
49 #define X86_FEATURE_IA64 ( 0*32+30) /* "ia64" IA-64 processor */
52 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
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/linux/drivers/gpu/drm/msm/registers/adreno/
H A Da4xx.xml1 <?xml version="1.0" encoding="UTF-8"?>
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
70 <!-- hmm, shifted one compared to a3xx?!? -->
88 <!-- beyond here it does not appear to be shifted -->
145 <!-- 0x00 .. 0x02 -->
147 <!-- 8-bit formats -->
154 <!-- 16-bit formats -->
157 <!-- 0x0a -->
160 <!-- 0x0c -->
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/linux/drivers/edac/
H A Dsb_edac.c1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Intel Sandy Bridge -EN/-EP/-EX Memory Controller kernel module
24 #include <asm/intel-family.h>
70 0x60, 0x68, 0x70, 0x78, 0x80, /* 0-4 */
71 0x88, 0x90, 0x98, 0xa0, 0xa8, /* 5-9 */
72 0xb0, 0xb8, 0xc0, 0xc8, 0xd0, /* 10-14 */
73 0xd8, 0xe0, 0xe8, 0xf0, 0xf8, /* 15-19 */
74 0x100, 0x108, 0x110, 0x118, /* 20-23 */
107 0x64, 0x6c, 0x74, 0x7c, 0x84, /* 0-4 */
108 0x8c, 0x94, 0x9c, 0xa4, 0xac, /* 5-9 */
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/linux/drivers/gpu/drm/radeon/
H A Datombios_crtc.c2 * Copyright 2007-8 Advanced Micro Devices, Inc.
36 #include "atom-bits.h"
42 struct drm_device *dev = crtc->dev; in atombios_overscan_setup()
43 struct radeon_device *rdev = dev->dev_private; in atombios_overscan_setup()
51 args.ucCRTC = radeon_crtc->crtc_id; in atombios_overscan_setup()
53 switch (radeon_crtc->rmx_type) { in atombios_overscan_setup()
55 args.usOverscanTop = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
56 args.usOverscanBottom = cpu_to_le16((adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2); in atombios_overscan_setup()
57 args.usOverscanLeft = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
58 args.usOverscanRight = cpu_to_le16((adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2); in atombios_overscan_setup()
[all …]

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