| /linux/drivers/gpu/drm/i915/gt/ |
| H A D | mock_engine.c | 60 static struct intel_ring *mock_ring(struct intel_engine_cs *engine) in mock_ring() argument
75 ring->vma = create_ring_vma(engine->gt->ggtt, PAGE_SIZE); in mock_ring()
93 static struct i915_request *first_request(struct mock_engine *engine) in first_request() argument
95 return list_first_entry_or_null(&engine->hw_queue, in first_request()
106 intel_engine_signal_breadcrumbs(request->engine); in advance()
111 struct mock_engine *engine = timer_container_of(engine, t, hw_delay); in hw_delay_complete() local
115 spin_lock_irqsave(&engine->hw_lock, flags); in hw_delay_complete()
118 request = first_request(engine); in hw_delay_complete()
126 while ((request = first_request(engine))) { in hw_delay_complete()
128 mod_timer(&engine->hw_delay, in hw_delay_complete()
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| H A D | intel_engine_cs.c | 260 * intel_engine_context_size() - return the size of the context for an engine
262 * @class: engine class
264 * Each engine class may require a different amount of space for a context
267 * Return: size (in bytes) of an engine class specific context image
358 static void __sprint_engine_name(struct intel_engine_cs *engine) in __sprint_engine_name() argument
361 * Before we know what the uABI name for this engine will be, in __sprint_engine_name()
362 * we still would like to keep track of this engine in the debug logs. in __sprint_engine_name()
365 GEM_WARN_ON(snprintf(engine->name, sizeof(engine->name), "%s'%u", in __sprint_engine_name()
366 intel_engine_class_repr(engine->class), in __sprint_engine_name()
367 engine->instance) >= sizeof(engine->name)); in __sprint_engine_name()
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| H A D | selftest_engine_heartbeat.c | 14 static void reset_heartbeat(struct intel_engine_cs *engine) in reset_heartbeat() argument
16 intel_engine_set_heartbeat(engine, in reset_heartbeat()
17 engine->defaults.heartbeat_interval_ms); in reset_heartbeat()
37 static int engine_sync_barrier(struct intel_engine_cs *engine) in engine_sync_barrier() argument
39 return timeline_sync(engine->kernel_context->timeline); in engine_sync_barrier()
90 static int __live_idle_pulse(struct intel_engine_cs *engine, in __live_idle_pulse() argument
96 GEM_BUG_ON(!intel_engine_pm_is_awake(engine)); in __live_idle_pulse()
106 err = i915_active_acquire_preallocate_barrier(&p->active, engine); in __live_idle_pulse()
116 GEM_BUG_ON(llist_empty(&engine->barrier_tasks)); in __live_idle_pulse()
118 err = fn(engine); in __live_idle_pulse()
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| H A D | intel_engine_pm.h | 17 intel_engine_pm_is_awake(const struct intel_engine_cs *engine) in intel_engine_pm_is_awake() argument
19 return intel_wakeref_is_active(&engine->wakeref); in intel_engine_pm_is_awake()
22 static inline void __intel_engine_pm_get(struct intel_engine_cs *engine) in __intel_engine_pm_get() argument
24 __intel_wakeref_get(&engine->wakeref); in __intel_engine_pm_get()
27 static inline void intel_engine_pm_get(struct intel_engine_cs *engine) in intel_engine_pm_get() argument
29 intel_wakeref_get(&engine->wakeref); in intel_engine_pm_get()
32 static inline bool intel_engine_pm_get_if_awake(struct intel_engine_cs *engine) in intel_engine_pm_get_if_awake() argument
34 return intel_wakeref_get_if_active(&engine->wakeref); in intel_engine_pm_get_if_awake()
37 static inline void intel_engine_pm_might_get(struct intel_engine_cs *engine) in intel_engine_pm_might_get() argument
39 if (!intel_engine_is_virtual(engine)) { in intel_engine_pm_might_get()
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| H A D | intel_engine_pm.c | 20 static void intel_gsc_idle_msg_enable(struct intel_engine_cs *engine) in intel_gsc_idle_msg_enable() argument
22 struct drm_i915_private *i915 = engine->i915; in intel_gsc_idle_msg_enable()
24 if (MEDIA_VER(i915) >= 13 && engine->id == GSC0) { in intel_gsc_idle_msg_enable()
25 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
29 intel_uncore_write(engine->gt->uncore, in intel_gsc_idle_msg_enable()
42 int type = intel_gt_coherent_map_type(ce->engine->gt, obj, true); in dbg_poison_ce()
60 struct intel_engine_cs *engine = in __engine_unpark() local
61 container_of(wf, typeof(*engine), wakeref); in __engine_unpark()
64 ENGINE_TRACE(engine, "\n"); in __engine_unpark()
66 engine->wakeref_track = intel_gt_pm_get(engine->gt); in __engine_unpark()
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| H A D | intel_execlists_submission.c | 24 * shouldn't we just need a set of those per engine command streamer? This is
26 * rings, the engine cs shifts to a new "ring buffer" with every context
41 * Now that ringbuffers belong per-context (and not per-engine, like before)
42 * and that contexts are uniquely tied to a given engine (and not reusable,
45 * - One ringbuffer per-engine inside each context.
46 * - One backing object per-engine inside each context.
50 * more complex, because we don't know at creation time which engine is going
55 * gets populated for a given engine once we receive an execbuffer. If later
57 * engine, we allocate/populate a new ringbuffer and context backing object and
74 * for the appropriate engine: this structure contains a copy of the context's
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| H A D | selftest_hangcheck.c | 104 hang_create_request(struct hang *h, struct intel_engine_cs *engine) in hang_create_request() argument
157 rq = igt_request_alloc(h->ctx, engine); in hang_create_request()
226 intel_gt_chipset_flush(engine->gt); in hang_create_request()
228 if (rq->engine->emit_init_breadcrumb) { in hang_create_request()
229 err = rq->engine->emit_init_breadcrumb(rq); in hang_create_request()
238 err = rq->engine->emit_bb_start(rq, i915_vma_offset(vma), PAGE_SIZE, flags); in hang_create_request()
288 struct intel_engine_cs *engine; in igt_hang_sanitycheck() local
299 for_each_engine(engine, gt, id) { in igt_hang_sanitycheck()
303 if (!intel_engine_can_store_dword(engine)) in igt_hang_sanitycheck()
306 rq = hang_create_request(&h, engine); in igt_hang_sanitycheck()
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| H A D | selftest_engine_pm.c | 76 struct intel_engine_cs *engine = ce->engine; in __measure_timestamps() local
77 u32 *sema = memset32(engine->status_page.addr + 1000, 0, 5); in __measure_timestamps()
78 u32 offset = i915_ggtt_offset(engine->status_page.vma); in __measure_timestamps()
96 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4000); in __measure_timestamps()
97 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4004); in __measure_timestamps()
102 cs = emit_srm(cs, RING_TIMESTAMP(engine->mmio_base), offset + 4016); in __measure_timestamps()
103 cs = emit_srm(cs, RING_CTX_TIMESTAMP(engine->mmio_base), offset + 4012); in __measure_timestamps()
108 intel_engine_flush_submission(engine); in __measure_timestamps()
132 engine->name, sema[1], sema[3], sema[0], sema[4]); in __measure_timestamps()
139 static int __live_engine_timestamps(struct intel_engine_cs *engine) in __live_engine_timestamps() argument
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| H A D | selftest_workarounds.c | 34 } engine[I915_NUM_ENGINES]; member
64 struct intel_engine_cs *engine; in reference_lists_init() local
73 for_each_engine(engine, gt, id) { in reference_lists_init()
74 struct i915_wa_list *wal = &lists->engine[id].wa_list; in reference_lists_init()
76 wa_init_start(wal, gt, "REF", engine->name); in reference_lists_init()
77 engine_init_workarounds(engine, wal); in reference_lists_init()
80 __intel_engine_init_ctx_wa(engine, in reference_lists_init()
81 &lists->engine[id].ctx_wa_list, in reference_lists_init()
89 struct intel_engine_cs *engine; in reference_lists_fini() local
92 for_each_engine(engine, gt, id) in reference_lists_fini()
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| H A D | sysfs_engines.c | 17 struct intel_engine_cs *engine; member
22 return container_of(kobj, struct kobj_engine, base)->engine; in kobj_to_engine()
82 __caps_show(struct intel_engine_cs *engine, in __caps_show() argument
89 switch (engine->class) { in __caps_show()
124 struct intel_engine_cs *engine = kobj_to_engine(kobj); in caps_show() local
126 return __caps_show(engine, engine->uabi_capabilities, buf, true); in caps_show()
145 struct intel_engine_cs *engine = kobj_to_engine(kobj); in max_spin_store() local
170 clamped = intel_clamp_max_busywait_duration_ns(engine, duration); in max_spin_store()
174 WRITE_ONCE(engine->props.max_busywait_duration_ns, duration); in max_spin_store()
182 struct intel_engine_cs *engine = kobj_to_engine(kobj); in max_spin_show() local
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| H A D | selftest_execlists.c | 27 #define CS_GPR(engine, n) ((engine)->mmio_base + 0x600 + (n) * 4) argument
45 static int wait_for_submit(struct intel_engine_cs *engine, in wait_for_submit() argument
50 tasklet_hi_schedule(&engine->sched_engine->tasklet); in wait_for_submit()
60 intel_engine_flush_submission(engine); in wait_for_submit()
61 if (!READ_ONCE(engine->execlists.pending[0]) && is_active(rq)) in wait_for_submit()
71 static int wait_for_reset(struct intel_engine_cs *engine, in wait_for_reset() argument
79 intel_engine_flush_submission(engine); in wait_for_reset()
81 if (READ_ONCE(engine->execlists.pending[0])) in wait_for_reset()
93 engine->name, in wait_for_reset()
103 engine->name, in wait_for_reset()
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| H A D | selftest_mocs.c | 24 static struct intel_context *mocs_context_create(struct intel_engine_cs *engine) in mocs_context_create() argument
28 ce = intel_context_create(engine); in mocs_context_create()
134 struct intel_gt *gt = rq->engine->gt; in read_mocs_table()
143 addr = mocs_offset(rq->engine); in read_mocs_table()
160 static int check_mocs_table(struct intel_engine_cs *engine, in check_mocs_table() argument
173 engine->name, i, **vaddr, expect); in check_mocs_table()
192 static int check_l3cc_table(struct intel_engine_cs *engine, in check_l3cc_table() argument
205 if (!mcr_range(engine->i915, reg) && **vaddr != expect) { in check_l3cc_table()
207 engine->name, i, **vaddr, expect); in check_l3cc_table()
238 if (!err && ce->engine->class == RENDER_CLASS) in check_mocs_engine()
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| H A D | intel_workarounds.c | 41 * - Engine workarounds: the list of these WAs is applied whenever the specific
42 * engine is reset. It's also possible that a set of engine classes share a
46 * driver is to tie those workarounds to the first compute/render engine that
47 * is registered. When executing with GuC submission, engine resets are
49 * written once, on engine initialization, and then passed to GuC, that
57 * engine's MMIO range but that are part of of the common RCS/CCS reset domain
89 * engine registers are restored in a context restore sequence. This is
337 static void gen6_ctx_workarounds_init(struct intel_engine_cs *engine, in gen6_ctx_workarounds_init() argument
346 static void gen7_ctx_workarounds_init(struct intel_engine_cs *engine, in gen7_ctx_workarounds_init() argument
363 static void gen8_ctx_workarounds_init(struct intel_engine_cs *engine, in gen8_ctx_workarounds_init() argument
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| H A D | selftest_engine_cs.c | 44 static i915_reg_t timestamp_reg(struct intel_engine_cs *engine) in timestamp_reg() argument
46 struct drm_i915_private *i915 = engine->i915; in timestamp_reg()
49 return RING_TIMESTAMP_UDW(engine->mmio_base); in timestamp_reg()
51 return RING_TIMESTAMP(engine->mmio_base); in timestamp_reg()
70 *cs++ = i915_mmio_reg_offset(timestamp_reg(rq->engine)); in write_timestamp()
86 obj = i915_gem_object_create_internal(ce->engine->i915, PAGE_SIZE); in create_empty_batch()
136 struct intel_engine_cs *engine; in perf_mi_bb_start() local
145 for_each_engine(engine, gt, id) { in perf_mi_bb_start()
146 struct intel_context *ce = engine->kernel_context; in perf_mi_bb_start()
151 if (GRAPHICS_VER(engine->i915) < 7 && engine->id != RCS0) in perf_mi_bb_start()
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| /linux/drivers/gpu/drm/nouveau/nvkm/core/ |
| H A D | engine.c | 24 #include <core/engine.h>
31 nvkm_engine_chsw_load(struct nvkm_engine *engine) in nvkm_engine_chsw_load() argument
33 if (engine->func->chsw_load) in nvkm_engine_chsw_load()
34 return engine->func->chsw_load(engine); in nvkm_engine_chsw_load()
39 nvkm_engine_reset(struct nvkm_engine *engine) in nvkm_engine_reset() argument
41 if (engine->func->reset) in nvkm_engine_reset()
42 return engine->func->reset(engine); in nvkm_engine_reset()
44 nvkm_subdev_fini(&engine->subdev, NVKM_POWEROFF); in nvkm_engine_reset()
45 return nvkm_subdev_init(&engine->subdev); in nvkm_engine_reset()
51 struct nvkm_engine *engine = *pengine; in nvkm_engine_unref() local
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sunxi_engine.h | 27 * This callback allows to prepare our engine for an atomic
34 void (*atomic_begin)(struct sunxi_engine *engine,
51 int (*atomic_check)(struct sunxi_engine *engine,
63 void (*commit)(struct sunxi_engine *engine,
71 * the layers supported by that engine.
81 struct sunxi_engine *engine);
87 * engine. This is useful only for the composite output.
91 void (*apply_color_correction)(struct sunxi_engine *engine);
97 * engine. This is useful only for the composite output.
101 void (*disable_color_correction)(struct sunxi_engine *engine);
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| /linux/drivers/video/fbdev/via/ |
| H A D | accel.c | 13 static int viafb_set_bpp(void __iomem *engine, u8 bpp) in viafb_set_bpp() argument
19 gemode = readl(engine + VIA_REG_GEMODE) & 0xfffffcfc; in viafb_set_bpp()
34 writel(gemode, engine + VIA_REG_GEMODE); in viafb_set_bpp()
39 static int hw_bitblt_1(void __iomem *engine, u8 op, u32 width, u32 height, in hw_bitblt_1() argument
79 ret = viafb_set_bpp(engine, dst_bpp); in hw_bitblt_1()
91 writel(tmp, engine + 0x08); in hw_bitblt_1()
100 writel(tmp, engine + 0x0C); in hw_bitblt_1()
108 writel(tmp, engine + 0x10); in hw_bitblt_1()
111 writel(fg_color, engine + 0x18); in hw_bitblt_1()
114 writel(bg_color, engine + 0x1C); in hw_bitblt_1()
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | allwinner,sun4i-a10-display-engine.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun4i-a10-display-engine.yaml#
7 title: Allwinner A10 Display Engine Pipeline
14 The display engine pipeline (and its entry point, since it can be
52 - allwinner,sun4i-a10-display-engine
53 - allwinner,sun5i-a10s-display-engine
54 - allwinner,sun5i-a13-display-engine
55 - allwinner,sun6i-a31-display-engine
56 - allwinner,sun6i-a31s-display-engine
57 - allwinner,sun7i-a20-display-engine
58 - allwinner,sun8i-a23-display-engine
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| /linux/drivers/gpu/drm/i915/selftests/ |
| H A D | i915_request.c | 54 struct intel_engine_cs *engine; in num_uabi_engines() local
58 for_each_uabi_engine(engine, i915) in num_uabi_engines()
255 request->engine->submit_request(request); in igt_request_rewind()
284 struct intel_engine_cs *engine; member
371 ce = i915_gem_context_get_engine(ctx, t->engine->legacy_idx); in __igt_breadcrumbs_smoketest()
412 t->engine->name); in __igt_breadcrumbs_smoketest()
415 intel_gt_set_wedged(t->engine->gt); in __igt_breadcrumbs_smoketest()
459 .engine = rcs0(i915), in mock_breadcrumbs_smoketest()
486 t.contexts[n] = mock_context(t.engine->i915, "mock"); in mock_breadcrumbs_smoketest()
571 struct intel_engine_cs *engine; in live_nop_request() local
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| H A D | intel_scheduler_helpers.c | 21 struct intel_engine_cs *engine; in intel_selftest_find_any_engine() local
24 for_each_engine(engine, gt, id) in intel_selftest_find_any_engine()
25 return engine; in intel_selftest_find_any_engine()
27 pr_err("No valid engine found!\n"); in intel_selftest_find_any_engine()
31 int intel_selftest_modify_policy(struct intel_engine_cs *engine, in intel_selftest_modify_policy() argument
37 saved->reset = engine->i915->params.reset; in intel_selftest_modify_policy()
38 saved->flags = engine->flags; in intel_selftest_modify_policy()
39 saved->timeslice = engine->props.timeslice_duration_ms; in intel_selftest_modify_policy()
40 saved->preempt_timeout = engine->props.preempt_timeout_ms; in intel_selftest_modify_policy()
46 * together with engine reset on pre-emption timeout. in intel_selftest_modify_policy()
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| /linux/drivers/gpu/drm/xe/ |
| H A D | xe_hw_engine_types.h | 13 /* See "Engine ID Definition" struct in the Icelake PRM */
69 * struct xe_hw_engine_class_intf - per hw engine class struct interface
71 * Contains all the hw engine properties per engine class.
82 /** @sched_props.set_job_timeout: Set job timeout in ms for engine */
84 /** @sched_props.job_timeout_min: Min job timeout in ms for engine */
86 /** @sched_props.job_timeout_max: Max job timeout in ms for engine */
104 * struct xe_hw_engine - Hardware engine
106 * Contains all the hardware engine state for physical instances.
109 /** @gt: GT structure this hw engine belongs to */
111 /** @name: name of this hw engine */
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/device/ |
| H A D | priv.h | 34 #include <engine/bsp.h>
35 #include <engine/ce.h>
36 #include <engine/cipher.h>
37 #include <engine/disp.h>
38 #include <engine/dma.h>
39 #include <engine/fifo.h>
40 #include <engine/gr.h>
41 #include <engine/mpeg.h>
42 #include <engine/mspdec.h>
43 #include <engine/msppp.h>
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/gr/ |
| H A D | base.c | 26 #include <engine/fifo.h>
56 nvkm_gr_chsw_load(struct nvkm_engine *engine) in nvkm_gr_chsw_load() argument
58 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_chsw_load()
65 nvkm_gr_tile(struct nvkm_engine *engine, int region, struct nvkm_fb_tile *tile) in nvkm_gr_tile() argument
67 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_tile()
91 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_oclass_get()
115 struct nvkm_gr *gr = nvkm_gr(oclass->engine); in nvkm_gr_cclass_new()
122 nvkm_gr_intr(struct nvkm_engine *engine) in nvkm_gr_intr() argument
124 struct nvkm_gr *gr = nvkm_gr(engine); in nvkm_gr_intr()
129 nvkm_gr_nonstall(struct nvkm_engine *engine) in nvkm_gr_nonstall() argument
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| /linux/drivers/gpu/drm/i915/gt/uc/ |
| H A D | intel_guc_submission.c | 104 * engine (sched_engine), thus only one of the contexts which share a
136 /* GuC Virtual Engine */
401 return gt_to_guc(ce->engine->gt); in ce_to_guc()
705 lockdep_assert_held(&rq->engine->sched_engine->lock); in __guc_add_request()
713 intel_engine_signal_breadcrumbs(ce->engine); in __guc_add_request()
1065 static void cs_irq_handler(struct intel_engine_cs *engine, u16 iir) in cs_irq_handler() argument
1068 intel_engine_signal_breadcrumbs(engine); in cs_irq_handler()
1136 intel_engine_signal_breadcrumbs(ce->engine); in scrub_guc_desc_for_outstanding_g2h()
1156 * GuC stores busyness stats for each engine at context in/out boundaries. A
1161 * __i915_pmu_event_read samples engine busyness. When sampling, if context id
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| /linux/drivers/gpu/drm/nouveau/nvkm/engine/dma/ |
| H A D | Kbuild | 2 nvkm-y += nvkm/engine/dma/base.o
3 nvkm-y += nvkm/engine/dma/nv04.o
4 nvkm-y += nvkm/engine/dma/nv50.o
5 nvkm-y += nvkm/engine/dma/gf100.o
6 nvkm-y += nvkm/engine/dma/gf119.o
7 nvkm-y += nvkm/engine/dma/gv100.o
9 nvkm-y += nvkm/engine/dma/user.o
10 nvkm-y += nvkm/engine/dma/usernv04.o
11 nvkm-y += nvkm/engine/dma/usernv50.o
12 nvkm-y += nvkm/engine/dma/usergf100.o
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