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Searched full:eus (Results 1 – 9 of 9) sorted by relevance

/linux/drivers/gpu/drm/i915/gt/
H A Dintel_sseu.h39 /* Maximum number of EUs that can exist within a subslice or DSS. */
81 /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */
H A Dintel_engine_cs.c504 /* features common between engines sharing EUs */ in intel_engine_setup()
/linux/drivers/gpu/drm/xe/
H A Dxe_ring_ops.c318 /* for engines that don't require any special HW handling (no EUs, no aux inval, etc) */
H A Dxe_exec_queue.c341 * other workload can use the EUs at the same time). On MTL this is done in __xe_exec_queue_init()
/linux/include/uapi/drm/
H A Di915_drm.h174 * the GPU's execution units (EUs).
2227 * Minimum/Maximum number of EUs to enable per subslice for the
3193 * subslice's EUs.
/linux/tools/include/uapi/drm/
H A Di915_drm.h
/linux/tools/perf/pmu-events/arch/x86/lunarlake/
H A Dpipeline.json2021 "BriefDescription": "Number of (shift) 1-cycle Uops dispatched/executed by any of the Shift Eus",
/linux/tools/perf/pmu-events/arch/x86/pantherlake/
H A Dpipeline.json2122 "BriefDescription": "Number of (shift) 1-cycle Uops dispatched/executed by any of the Shift Eus",
/linux/tools/perf/pmu-events/arch/x86/arrowlake/
H A Dpipeline.json2578 "BriefDescription": "Number of (shift) 1-cycle Uops dispatched/executed by any of the Shift Eus",