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/linux/tools/testing/selftests/tc-testing/tc-tests/qdiscs/
H A Detf.json4 "name": "Create ETF with default setting",
7 "etf"
14 "cmdUnderTest": "$TC qdisc add dev $DUMMY handle 1: root etf clockid CLOCK_TAI",
17 …"matchPattern": "qdisc etf 1: root refcnt [0-9]+ clockid TAI delta 0 offload off deadline_mode off…
25 "name": "Create ETF with delta nanos setting",
28 "etf"
35 "cmdUnderTest": "$TC qdisc add dev $DUMMY handle 1: root etf delta 100 clockid CLOCK_TAI",
38 …"matchPattern": "qdisc etf 1: root refcnt [0-9]+ clockid TAI delta 100 offload off deadline_mode o…
46 "name": "Create ETF with deadline_mode setting",
49 "etf"
[all …]
/linux/net/sched/
H A Dsch_etf.c299 struct tc_etf_qopt_offload etf = { }; in etf_disable_offload() local
310 etf.queue = q->queue; in etf_disable_offload()
311 etf.enable = 0; in etf_disable_offload()
313 err = ops->ndo_setup_tc(dev, TC_SETUP_QDISC_ETF, &etf); in etf_disable_offload()
315 pr_warn("Couldn't disable ETF offload for queue %d\n", in etf_disable_offload()
316 etf.queue); in etf_disable_offload()
323 struct tc_etf_qopt_offload etf = { }; in etf_enable_offload() local
327 NL_SET_ERR_MSG(extack, "Specified device does not support ETF offload"); in etf_enable_offload()
331 etf.queue = q->queue; in etf_enable_offload()
332 etf.enable = 1; in etf_enable_offload()
[all …]
H A DKconfig157 tristate "Earliest TxTime First (ETF)"
159 Say Y here if you want to use the Earliest TxTime First (ETF) packet
/linux/Documentation/devicetree/bindings/arm/
H A Darm,coresight-tmc.yaml24 FIFO(ETF) and Embedded Trace Router(ETR) configurations. The configuration
25 mode (ETB, ETF, ETR) is discovered at boot time when the device is probed.
101 and ETF configurations.
/linux/drivers/hwtracing/coresight/
H A Dcoresight-tmc-etf.c219 * /dev/xyz.{etf|etb} interface. See tmc_read_unprepare_etf() for in tmc_enable_etf_sink_sysfs()
262 * No need to continue if the ETB/ETF is already operated in tmc_enable_etf_sink_perf()
325 dev_dbg(&csdev->dev, "TMC-ETB/ETF enabled\n"); in tmc_enable_etf_sink()
356 dev_dbg(&csdev->dev, "TMC-ETB/ETF disabled\n"); in tmc_disable_etf_sink()
387 dev_dbg(&csdev->dev, "TMC-ETF enabled\n"); in tmc_enable_etf_link()
414 dev_dbg(&csdev->dev, "TMC-ETF disabled\n"); in tmc_disable_etf_link()
701 * The ETB/ETF is not tracing and the buffer was just read. in tmc_read_unprepare_etb()
H A Dcoresight-tmc.h177 * @buf: Snapshot of the trace data for ETF/ETB.
179 * @len: size of the available trace for ETF/ETB.
267 /* ETB/ETF functions */
H A DMakefile31 coresight-tmc-y := coresight-tmc-core.o coresight-tmc-etf.o \
H A Dcoresight-tmc-core.c429 * AXI master in place of the embedded SRAM of ETB/ETF. in tmc_etr_setup_caps()
640 /* Coresight SoC 600 TMC-ETF */
725 {"ARMHC97C", 0, 0, 0}, /* ARM CoreSight SoC-400 TMC, SoC-600 ETF/ETB */
H A Dcoresight-core.c387 * ETF devices are tricky... They can be a link or a sink, in coresight_disable_path_from()
388 * depending on how they are configured. If an ETF has been
468 * ETF devices are tricky... They can be a link or a sink, in coresight_enable_path()
469 * depending on how they are configured. If an ETF has been in coresight_enable_path()
/linux/tools/testing/selftests/net/
H A Dso_txtime.sh93 if ip netns exec "${NS1}" tc qdisc replace dev "${DEV}" root etf clockid CLOCK_TAI delta 400000; th…
100 echo "tc ($(tc -V)) does not support qdisc etf. skipping"
/linux/arch/arm64/boot/dts/hisilicon/
H A Dhi3660-coresight.dtsi131 etf@ec802000 {
273 etf@ed002000 {
365 etf@ec036000 {
H A Dhi6220-coresight.dtsi38 etf@f6402000 {
/linux/arch/arm64/boot/dts/sprd/
H A Dsc9860.dtsi464 etf@11003000 { /* ETF on Cluster0 */
489 etf@11004000 { /* ETF on Cluster1 */
H A Dums512.dtsi484 /* SoC ETF */
551 /* AP-CPU ETF for little cores */
552 etf@3e002000 {
577 /* AP-CPU ETF for big cores */
578 etf@3e003000 {
H A Dsc9836.dtsi47 etf@10003000 {
/linux/arch/arm64/boot/dts/arm/
H A Djuno-r2-scmi.dts9 etf@20140000 {
H A Djuno-r1-scmi.dts9 etf@20140000 {
H A Djuno-cs-r1r2.dtsi26 etf_sys1: etf@20140000 { /* etf1 */
H A Djuno-scmi.dtsi2 etf@20010000 {
/linux/Documentation/trace/coresight/
H A Dcoresight.rst113 TMC-ETF:
125 ETBv1.0, ETB1.1, TPIU, TMC-ETF
210 20010000.etf 20040000.funnel 20100000.stm 22040000.etm
278 <file details> out:0 -> ../../../20010000.etf/tmc_etf0
292 <file details> in:0 -> ../../../20010000.etf/tmc_etf0
293 <file details> in:1 -> ../../../20140000.etf/tmc_etf1
325 <file details> tmc_etf0 -> ../../../20010000.etf/tmc_etf0
/linux/drivers/accel/habanalabs/goya/
H A Dgoya_coresight.c310 dev_err(hdev->dev, "Invalid register index in ETF\n"); in goya_config_etf()
332 "Failed to %s ETF on timeout, error %d\n", in goya_config_etf()
340 "Failed to %s ETF on timeout, error %d\n", in goya_config_etf()
707 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i); in goya_halt_coresight()
/linux/drivers/accel/habanalabs/gaudi/
H A Dgaudi_coresight.c477 dev_err(hdev->dev, "Invalid register index in ETF\n"); in gaudi_config_etf()
499 "Failed to %s ETF on timeout, error %d\n", in gaudi_config_etf()
507 "Failed to %s ETF on timeout, error %d\n", in gaudi_config_etf()
912 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i); in gaudi_halt_coresight()
/linux/drivers/accel/habanalabs/gaudi2/
H A Dgaudi2_coresight.c47 * @etf_id: etf id - index in debug_etf_regs
2068 dev_err(hdev->dev, "Invalid register index in ETF\n"); in gaudi2_config_etf()
2082 * for doing do need to read ETF STS register and check in gaudi2_config_etf()
2108 dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", in gaudi2_config_etf()
2115 dev_err(hdev->dev, "Failed to %s ETF on timeout, error %d\n", in gaudi2_config_etf()
2591 dev_err(hdev->dev, "halt ETF failed, %d/%d\n", rc, i); in gaudi2_halt_coresight()
H A Dgaudi2_coresight_regs.h119 /* ETF Offsets - same offsets for all etfs */
/linux/tools/testing/selftests/drivers/net/ocelot/
H A Dpsfp.sh160 tc qdisc replace dev ${if_name} parent 100:$((${STREAM_PRIO} + 1)) etf \

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