| /linux/drivers/memory/tegra/ |
| H A D | tegra20-emc.c | 216 * There are multiple sources in the EMC driver which could request
237 struct tegra_emc *emc = data; in tegra20_emc_isr() local
241 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra20_emc_isr()
247 dev_err_ratelimited(emc->dev, in tegra20_emc_isr()
251 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra20_emc_isr()
256 static struct emc_timing *tegra20_emc_find_timing(struct tegra_emc *emc, in tegra20_emc_find_timing() argument
262 for (i = 0; i < emc->num_timings; i++) { in tegra20_emc_find_timing()
263 if (emc->timings[i].rate >= rate) { in tegra20_emc_find_timing()
264 timing = &emc->timings[i]; in tegra20_emc_find_timing()
270 dev_err(emc->dev, "no timing for rate %lu\n", rate); in tegra20_emc_find_timing()
[all …]
|
| H A D | tegra30-emc.c | 5 * Based on downstream driver from NVIDIA and tegra124-emc.c
387 * There are multiple sources in the EMC driver which could request
398 static int emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
418 struct tegra_emc *emc = data; in tegra30_emc_isr() local
422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra30_emc_isr()
428 dev_err_ratelimited(emc->dev, in tegra30_emc_isr()
432 writel_relaxed(status, emc in tegra30_emc_isr()
437 emc_find_timing(struct tegra_emc * emc,unsigned long rate) emc_find_timing() argument
458 emc_dqs_preset(struct tegra_emc * emc,struct emc_timing * timing,bool * schmitt_to_vref) emc_dqs_preset() argument
501 emc_prepare_mc_clk_cfg(struct tegra_emc * emc,unsigned long rate) emc_prepare_mc_clk_cfg() argument
523 emc_prepare_timing_change(struct tegra_emc * emc,unsigned long rate) emc_prepare_timing_change() argument
792 emc_complete_timing_change(struct tegra_emc * emc,unsigned long rate) emc_complete_timing_change() argument
843 emc_unprepare_timing_change(struct tegra_emc * emc,unsigned long rate) emc_unprepare_timing_change() argument
858 struct tegra_emc *emc = container_of(nb, struct tegra_emc, clk_nb); emc_clk_change_notify() local
888 load_one_timing_from_dt(struct tegra_emc * emc,struct emc_timing * timing,struct device_node * node) load_one_timing_from_dt() argument
956 emc_check_mc_timings(struct tegra_emc * emc) emc_check_mc_timings() argument
979 emc_load_timings_from_dt(struct tegra_emc * emc,struct device_node * node) emc_load_timings_from_dt() argument
1023 emc_find_node_by_ram_code(struct tegra_emc * emc) emc_find_node_by_ram_code() argument
1056 emc_read_lpddr_mode_register(struct tegra_emc * emc,unsigned int emem_dev,unsigned int register_addr,unsigned int * register_data) emc_read_lpddr_mode_register() argument
1092 emc_read_lpddr_sdram_info(struct tegra_emc * emc,unsigned int emem_dev) emc_read_lpddr_sdram_info() argument
1115 emc_setup_hw(struct tegra_emc * emc) emc_setup_hw() argument
1196 struct tegra_emc *emc = arg; emc_round_rate() local
1231 tegra30_emc_rate_requests_init(struct tegra_emc * emc) tegra30_emc_rate_requests_init() argument
1241 emc_request_rate(struct tegra_emc * emc,unsigned long new_min_rate,unsigned long new_max_rate,enum emc_rate_request_type type) emc_request_rate() argument
1282 emc_set_min_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_min_rate() argument
1295 emc_set_max_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_max_rate() argument
1333 tegra30_emc_validate_rate(struct tegra_emc * emc,unsigned long rate) tegra30_emc_validate_rate() argument
1346 struct tegra_emc *emc = s->private; tegra30_emc_debug_available_rates_show() local
1363 struct tegra_emc *emc = data; tegra30_emc_debug_min_rate_get() local
1372 struct tegra_emc *emc = data; tegra30_emc_debug_min_rate_set() local
1393 struct tegra_emc *emc = data; tegra30_emc_debug_max_rate_get() local
1402 struct tegra_emc *emc = data; tegra30_emc_debug_max_rate_set() local
1421 tegra30_emc_debugfs_init(struct tegra_emc * emc) tegra30_emc_debugfs_init() argument
1498 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); emc_icc_set() local
1521 tegra30_emc_interconnect_init(struct tegra_emc * emc) tegra30_emc_interconnect_init() argument
1577 struct tegra_emc *emc = data; devm_tegra30_emc_unreg_clk_notifier() local
1582 tegra30_emc_init_clk(struct tegra_emc * emc) tegra30_emc_init_clk() argument
1614 struct tegra_emc *emc; tegra30_emc_probe() local
1683 struct tegra_emc *emc = dev_get_drvdata(dev); tegra30_emc_suspend() local
1704 struct tegra_emc *emc = dev_get_drvdata(dev); tegra30_emc_resume() local
[all...] |
| H A D | tegra210-emc-core.c | 21 #include "tegra210-emc.h"
69 next->trim_perch_regs[EMC ## chan ## \
561 struct tegra210_emc *emc = timer_container_of(emc, timer, training); in tegra210_emc_train() local
564 if (!emc->last) in tegra210_emc_train()
567 spin_lock_irqsave(&emc->lock, flags); in tegra210_emc_train()
569 if (emc->sequence->periodic_compensation) in tegra210_emc_train()
570 emc->sequence->periodic_compensation(emc); in tegra210_emc_train()
572 spin_unlock_irqrestore(&emc->lock, flags); in tegra210_emc_train()
574 mod_timer(&emc->training, in tegra210_emc_train()
575 jiffies + msecs_to_jiffies(emc->training_interval)); in tegra210_emc_train()
[all …]
|
| H A D | tegra186-emc.c | 43 * to control the EMC frequency. The top-level directory can be found here:
45 * /sys/kernel/debug/emc
50 * EMC frequencies.
54 * configured EMC frequency, this will cause the frequency to be
59 * the value is lower than the currently configured EMC frequency, this
64 static bool tegra186_emc_validate_rate(struct tegra186_emc *emc, in tegra186_emc_validate_rate()
69 for (i = 0; i < emc->num_dvfs; i++) in tegra186_emc_validate_rate()
70 if (rate == emc->dvfs[i].rate) in tegra186_emc_validate_rate()
79 struct tegra186_emc *emc = s->private; in tegra186_emc_debug_available_rates_show()
83 for (i = 0; i < emc in tegra186_emc_debug_available_rates_show()
63 tegra186_emc_validate_rate(struct tegra186_emc * emc,unsigned long rate) tegra186_emc_validate_rate() argument
78 struct tegra186_emc *emc = s->private; tegra186_emc_debug_available_rates_show() local
95 struct tegra186_emc *emc = data; tegra186_emc_debug_min_rate_get() local
104 struct tegra186_emc *emc = data; tegra186_emc_debug_min_rate_set() local
125 struct tegra186_emc *emc = data; tegra186_emc_debug_max_rate_get() local
134 struct tegra186_emc *emc = data; tegra186_emc_debug_max_rate_set() local
153 tegra186_emc_get_emc_dvfs_latency(struct tegra186_emc * emc) tegra186_emc_get_emc_dvfs_latency() argument
258 tegra186_emc_interconnect_init(struct tegra186_emc * emc) tegra186_emc_interconnect_init() argument
312 struct tegra186_emc *emc; tegra186_emc_probe() local
376 struct tegra186_emc *emc = platform_get_drvdata(pdev); tegra186_emc_remove() local
[all...] |
| H A D | tegra124-emc.c | 507 * There are multiple sources in the EMC driver which could request
518 static void emc_ccfifo_writel(struct tegra_emc *emc, u32 value, in emc_ccfifo_writel() argument
521 writel(value, emc->regs + EMC_CCFIFO_DATA); in emc_ccfifo_writel()
522 writel(offset, emc->regs + EMC_CCFIFO_ADDR); in emc_ccfifo_writel()
525 static void emc_seq_update_timing(struct tegra_emc *emc) in emc_seq_update_timing() argument
530 writel(1, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
533 value = readl(emc->regs + EMC_STATUS); in emc_seq_update_timing()
539 dev_err(emc->dev, "timing update timed out\n"); in emc_seq_update_timing()
542 static void emc_seq_disable_auto_cal(struct tegra_emc *emc) in emc_seq_disable_auto_cal() argument
547 writel(0, emc in emc_seq_disable_auto_cal()
559 emc_seq_wait_clkchange(struct tegra_emc * emc) emc_seq_wait_clkchange() argument
574 tegra124_emc_find_timing(struct tegra_emc * emc,unsigned long rate) tegra124_emc_find_timing() argument
595 tegra124_emc_prepare_timing_change(struct tegra_emc * emc,unsigned long rate) tegra124_emc_prepare_timing_change() argument
823 tegra124_emc_complete_timing_change(struct tegra_emc * emc,unsigned long rate) tegra124_emc_complete_timing_change() argument
880 emc_read_current_timing(struct tegra_emc * emc,struct emc_timing * timing) emc_read_current_timing() argument
899 emc_init(struct tegra_emc * emc) emc_init() argument
918 load_one_timing_from_dt(struct tegra_emc * emc,struct emc_timing * timing,struct device_node * node) load_one_timing_from_dt() argument
989 tegra124_emc_load_timings_from_dt(struct tegra_emc * emc,struct device_node * node) tegra124_emc_load_timings_from_dt() argument
1044 tegra124_emc_rate_requests_init(struct tegra_emc * emc) tegra124_emc_rate_requests_init() argument
1054 emc_request_rate(struct tegra_emc * emc,unsigned long new_min_rate,unsigned long new_max_rate,enum emc_rate_request_type type) emc_request_rate() argument
1095 emc_set_min_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_min_rate() argument
1108 emc_set_max_rate(struct tegra_emc * emc,unsigned long rate,enum emc_rate_request_type type) emc_set_max_rate() argument
1146 tegra124_emc_validate_rate(struct tegra_emc * emc,unsigned long rate) tegra124_emc_validate_rate() argument
1160 struct tegra_emc *emc = s->private; tegra124_emc_debug_available_rates_show() local
1178 struct tegra_emc *emc = data; tegra124_emc_debug_min_rate_get() local
1187 struct tegra_emc *emc = data; tegra124_emc_debug_min_rate_set() local
1208 struct tegra_emc *emc = data; tegra124_emc_debug_max_rate_get() local
1217 struct tegra_emc *emc = data; tegra124_emc_debug_max_rate_set() local
1236 emc_debugfs_init(struct device * dev,struct tegra_emc * emc) emc_debugfs_init() argument
1313 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); emc_icc_set() local
1337 tegra124_emc_interconnect_init(struct tegra_emc * emc) tegra124_emc_interconnect_init() argument
1386 tegra124_emc_opp_table_init(struct tegra_emc * emc) tegra124_emc_opp_table_init() argument
1436 struct tegra_emc *emc; tegra124_emc_probe() local
[all...] |
| H A D | tegra210-emc-cc-r21021.c | 14 #include "tegra210-emc.h"
36 #define emc_dbg(emc, flags, ...) dev_dbg(emc->dev, __VA_ARGS__) argument
108 emc_dbg(emc, EMA_UPDATES, "%s: (s=%u) EMA: %u\n", \
133 static void tegra210_emc_get_clktree_delay(struct tegra210_emc *emc, in tegra210_emc_get_clktree_delay() argument
136 struct tegra210_emc_timing *curr = emc->last; in tegra210_emc_get_clktree_delay()
145 tegra210_emc_start_periodic_compensation(emc); in tegra210_emc_get_clktree_delay()
148 for (d = 0; d < emc->num_devices; d++) { in tegra210_emc_get_clktree_delay()
150 msb = tegra210_emc_mrr_read(emc, 2 - d, 19); in tegra210_emc_get_clktree_delay()
151 lsb = tegra210_emc_mrr_read(emc, 2 - d, 18); in tegra210_emc_get_clktree_delay()
153 for (c = 0; c < emc->num_channels; c++) { in tegra210_emc_get_clktree_delay()
[all …]
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| H A D | tegra210-emc-table.c | 8 #include "tegra210-emc.h"
15 struct tegra210_emc *emc = dev_get_drvdata(dev); in tegra210_emc_table_device_init() local
21 dev_err(dev, "failed to map EMC table\n"); in tegra210_emc_table_device_init()
33 if (emc->derated) { in tegra210_emc_table_device_init()
34 dev_warn(dev, "excess EMC table '%s'\n", rmem->name); in tegra210_emc_table_device_init()
38 if (emc->nominal) { in tegra210_emc_table_device_init()
39 if (count != emc->num_timings) { in tegra210_emc_table_device_init()
41 count, emc->num_timings); in tegra210_emc_table_device_init()
46 emc->derated = timings; in tegra210_emc_table_device_init()
48 emc in tegra210_emc_table_device_init()
63 struct tegra210_emc *emc = dev_get_drvdata(dev); tegra210_emc_table_device_release() local
[all...] |
| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra124-jetson-tk1-emc.dtsi | 7 emc-timings-3 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
70 clock-names = "emc-parent";
[all …]
|
| H A D | tegra124-apalis-emc.dtsi | 11 emc-timings-1 {
18 clock-names = "emc-parent";
25 clock-names = "emc-parent";
32 clock-names = "emc-parent";
39 clock-names = "emc-parent";
46 clock-names = "emc-parent";
53 clock-names = "emc-parent";
60 clock-names = "emc-parent";
67 clock-names = "emc-parent";
74 clock-names = "emc-parent";
[all …]
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| H A D | tegra124-nyan-blaze-emc.dtsi | 7 emc-timings-1 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
72 clock-names = "emc-parent";
[all …]
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| H A D | tegra30-asus-tf300t.dts | 146 emc-timings-0 {
211 emc-timings-1 {
276 emc-timings-2 {
343 emc-timings-0 {
350 nvidia,emc-auto-cal-interval = <0x001fffff>;
351 nvidia,emc-mode-1 = <0x80100003>;
352 nvidia,emc-mode-2 = <0x80200008>;
353 nvidia,emc-mode-reset = <0x80001221>;
354 nvidia,emc-zcal-cnt-long = <0x00000040>;
355 nvidia,emc-cfg-dyn-self-ref;
[all …]
|
| H A D | tegra30-asus-tf300tg.dts | 220 emc-timings-0 {
285 emc-timings-1 {
350 emc-timings-2 {
417 emc-timings-0 {
424 nvidia,emc-auto-cal-interval = <0x001fffff>;
425 nvidia,emc-mode-1 = <0x80100003>;
426 nvidia,emc-mode-2 = <0x80200048>;
427 nvidia,emc-mode-reset = <0x80001221>;
428 nvidia,emc-zcal-cnt-long = <0x00000040>;
429 nvidia,emc-cfg-dyn-self-ref;
[all …]
|
| H A D | tegra30-asus-tf700t.dts | 141 emc-timings-0 {
206 emc-timings-1 {
273 emc-timings-0 {
280 nvidia,emc-auto-cal-interval = <0x001fffff>;
281 nvidia,emc-mode-1 = <0x80100003>;
282 nvidia,emc-mode-2 = <0x80200008>;
283 nvidia,emc-mode-reset = <0x80001221>;
284 nvidia,emc-zcal-cnt-long = <0x00000040>;
285 nvidia,emc-cfg-dyn-self-ref;
286 nvidia,emc-cfg-periodic-qrst;
[all …]
|
| H A D | tegra30-asus-tf201.dts | 112 emc-timings-0 {
167 emc-timings-1 {
224 emc-timings-0 {
231 nvidia,emc-auto-cal-interval = <0x001fffff>;
232 nvidia,emc-mode-1 = <0x00010022>;
233 nvidia,emc-mode-2 = <0x00020001>;
234 nvidia,emc-mode-reset = <0x00000000>;
235 nvidia,emc-zcal-cnt-long = <0x00000009>;
236 nvidia,emc-cfg-periodic-qrst;
238 nvidia,emc-configuration = < 0x00000001
[all …]
|
| H A D | tegra30-asus-tf300tl.dts | 240 emc-timings-0 {
305 emc-timings-1 {
372 emc-timings-0 {
379 nvidia,emc-auto-cal-interval = <0x001fffff>;
380 nvidia,emc-mode-1 = <0x80100003>;
381 nvidia,emc-mode-2 = <0x80200048>;
382 nvidia,emc-mode-reset = <0x80001221>;
383 nvidia,emc-zcal-cnt-long = <0x00000040>;
384 nvidia,emc-cfg-dyn-self-ref;
385 nvidia,emc-cfg-periodic-qrst;
[all …]
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| H A D | tegra124-nyan-big-emc.dtsi | 7 emc-timings-1 {
14 clock-names = "emc-parent";
21 clock-names = "emc-parent";
28 clock-names = "emc-parent";
35 clock-names = "emc-parent";
42 clock-names = "emc-parent";
49 clock-names = "emc-parent";
56 clock-names = "emc-parent";
63 clock-names = "emc-parent";
70 clock-names = "emc-parent";
[all …]
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| H A D | tegra124-xiaomi-mocha.dts | 105 emc-timings-0 {
112 clock-names = "emc-parent";
119 clock-names = "emc-parent";
126 clock-names = "emc-parent";
133 clock-names = "emc-parent";
140 clock-names = "emc-parent";
147 clock-names = "emc-parent";
154 clock-names = "emc-parent";
161 clock-names = "emc-parent";
168 clock-names = "emc-parent";
[all …]
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| H A D | tegra30-lg-p895.dts | 149 emc-timings-2 {
226 emc-timings-2 {
233 nvidia,emc-auto-cal-interval = <0x001fffff>;
234 nvidia,emc-mode-1 = <0x00010022>;
235 nvidia,emc-mode-2 = <0x00020001>;
236 nvidia,emc-mode-reset = <0x00000000>;
237 nvidia,emc-zcal-cnt-long = <0x00000009>;
238 nvidia,emc-cfg-periodic-qrst;
240 nvidia,emc-configuration = < 0x00000000
268 nvidia,emc
[all...] |
| H A D | tegra30-pegatron-chagall.dts | 1543 emc-timings-0 {
1598 emc-timings-1 {
1653 emc-timings-2 {
1708 emc-timings-3 {
1765 emc-timings-0 {
1772 nvidia,emc-auto-cal-interval = <0x001fffff>;
1773 nvidia,emc-mode-1 = <0x00010022>;
1774 nvidia,emc-mode-2 = <0x00020001>;
1775 nvidia,emc-mode-reset = <0x00000000>;
1776 nvidia,emc-zcal-cnt-long = <0x00000009>;
[all …]
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| H A D | tegra30-asus-nexus7-grouper-memory-timings.dtsi | 5 emc-timings-0 {
159 emc-timings-1 {
315 emc-timings-0 {
321 nvidia,emc-auto-cal-interval = <0x001fffff>;
322 nvidia,emc-mode-1 = <0x80100003>;
323 nvidia,emc-mode-2 = <0x80200008>;
324 nvidia,emc-mode-reset = <0x80001221>;
325 nvidia,emc-zcal-cnt-long = <0x00000040>;
326 nvidia,emc-cfg-dyn-self-ref;
327 nvidia,emc-cfg-periodic-qrst;
[all …]
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| /linux/drivers/clk/tegra/ |
| H A D | clk-tegra20-emc.c | 3 * Based on drivers/clk/tegra/clk-emc.c
10 #define pr_fmt(fmt) "tegra-emc-clk: " fmt
57 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_recalc_rate() local
60 val = readl_relaxed(emc->reg); in emc_recalc_rate()
68 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_get_parent() local
70 return readl_relaxed(emc->reg) >> CLK_SOURCE_EMC_2X_CLK_SRC_SHIFT; in emc_get_parent()
75 struct tegra_clk_emc *emc = to_tegra_clk_emc(hw); in emc_set_parent() local
78 val = readl_relaxed(emc->reg); in emc_set_parent()
84 if (index == EMC_SRC_PLL_M && div == 0 && emc->want_low_jitter) in emc_set_parent()
89 if (emc->mc_same_freq) in emc_set_parent()
[all …]
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| H A D | clk-tegra210-emc.c | 53 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_get_parent() local
57 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_get_parent()
66 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_recalc_rate() local
74 * This can lead to wrong results being reported for the EMC clock if in tegra210_clk_emc_recalc_rate()
75 * the parent and/or parent rate have changed as part of the EMC rate in tegra210_clk_emc_recalc_rate()
81 value = readl_relaxed(emc->regs + CLK_SOURCE_EMC); in tegra210_clk_emc_recalc_rate()
92 struct tegra210_clk_emc *emc = to_tegra210_clk_emc(hw); in tegra210_clk_emc_determine_rate() local
93 struct tegra210_clk_emc_provider *provider = emc->provider; in tegra210_clk_emc_determine_rate()
115 static struct clk *tegra210_clk_emc_find_parent(struct tegra210_clk_emc *emc, in tegra210_clk_emc_find_parent() argument
118 struct clk_hw *parent = clk_hw_get_parent_by_index(&emc->hw, index); in tegra210_clk_emc_find_parent()
[all …]
|
| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | nvidia,tegra124-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-emc.yaml#
14 The EMC interfaces with the off-chip SDRAM to service the request stream
19 const: nvidia,tegra124-emc
30 - const: emc
51 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-config:
77 nvidia,emc-auto-cal-config2:
83 nvidia,emc-auto-cal-config3:
89 nvidia,emc-auto-cal-interval:
96 nvidia,emc-bgbias-ctl0:
[all …]
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| H A D | nvidia,tegra30-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml#
15 The EMC interfaces with the off-chip SDRAM to service the request stream
16 sent from Memory Controller. The EMC also has various performance-affecting
18 settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2,
23 const: nvidia,tegra30-emc
53 "^emc-timings-[0-9]+$":
71 nvidia,emc-auto-cal-interval:
78 nvidia,emc-mode-1:
83 nvidia,emc-mode-2:
88 nvidia,emc-mode-reset:
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| H A D | nvidia,tegra20-emc.yaml | 4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
15 The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
16 service the request stream sent from Memory Controller. The EMC also has
18 parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
23 const: nvidia,tegra20-emc
61 If present, the emc-tables@ sub-nodes will be addressed.
64 emc-table:
68 const: nvidia,tegra20-emc-table
82 nvidia,emc-registers:
84 EMC timing characterization data. These are the registers
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