| /freebsd/sys/arm64/arm64/ |
| H A D | hyp_stub.S | 59 vector_stub_el1h_sync /* Synchronous 64-bit EL1 */
60 vempty /* IRQ 64-bit EL1 */
61 vempty /* FIQ 64-bit EL1 */
62 vempty /* SError 64-bit EL1 */
64 vempty /* Synchronous 32-bit EL1 */
65 vempty /* IRQ 32-bit EL1 */
66 vempty /* FIQ 32-bit EL1 */
67 vempty /* SError 32-bit EL1 */
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| H A D | locore.S | 346 * - If in EL1 continue in EL1
349 * - Configure EL2 to support running the kernel at EL1 and exit to that
425 * than EL1.
448 /* Enable SPE at EL1 via Monitor Debug Configuration Register */
455 /* Enable access to the physical timers at EL1 */
483 orr x2, x2, #ICC_SRE_EL2_EN /* Enable access from insecure EL1 */
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| /freebsd/sys/arm64/vmm/ |
| H A D | vmm_nvhe_exception.S | 45 vector hyp_init /* Synchronous 64-bit EL1 */
46 vempty /* IRQ 64-bit EL1 */
47 vempty /* FIQ 64-bit EL1 */
48 vempty /* Error 64-bit EL1 */
50 vempty /* Synchronous 32-bit EL1 */
51 vempty /* IRQ 32-bit EL1 */
52 vempty /* FIQ 32-bit EL1 */
53 vempty /* Error 32-bit EL1 */
85 /* Use the same memory attributes as EL1 */
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| H A D | vmm_hyp_exception.S | 162 vector el2_el1_sync64 /* Synchronous 64-bit EL1 */
163 vector el2_el1_irq64 /* IRQ 64-bit EL1 */
164 vector el2_el1_fiq64 /* FIQ 64-bit EL1 */
165 vector el2_el1_error64 /* Error 64-bit EL1 */
167 vempty /* Synchronous 32-bit EL1 */
168 vempty /* IRQ 32-bit EL1 */
169 vempty /* FIQ 32-bit EL1 */
170 vempty /* Error 32-bit EL1 */
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| H A D | vmm_reset.c | 124 * HCR_RW: use AArch64 for EL1 in reset_vm_el2_regs()
186 /* Use the EL1 stack when taking exceptions to EL1 */ in reset_vm_el2_regs()
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| H A D | arm64.h | 49 * EL1 control registers.
55 uint64_t tpidr_el1; /* EL1 Software ID Register */
|
| /freebsd/lib/libpmc/pmu-events/arch/arm64/arm/cortex-a75/ |
| H A D | mmu.json | 9 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
12 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
15 …lk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1",
18 …alk handled by the MMU. This event is not counted when it is accessible from Non-secure EL0 or EL1"
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| H A D | exception.json | 12 …ructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1",
15 …tructions are excluded. This event is not counted when it is accessible from Non-secure EL0 or EL1"
|
| /freebsd/contrib/netbsd-tests/lib/libcurses/ |
| H A D | atf.terminfo | 11 ed=ed, el=el, el1=el1, enacs=enacs, flash=flash, home=home,
|
| /freebsd/cddl/contrib/opensolaris/tools/ctf/cvt/ |
| H A D | alist.c | 66 alist_el_t *el1 = arg1; in alist_cmp() local
68 return ((uintptr_t)el1->ale_name != (uintptr_t)el2->ale_name); in alist_cmp()
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| H A D | merge.c | 308 elist_t *el1 = stdp->t_emem; in equiv_enum() local
311 while (el1 && el2) { in equiv_enum()
312 if (el1->el_number != el2->el_number || in equiv_enum()
313 strcmp(el1->el_name, el2->el_name) != 0) in equiv_enum()
316 el1 = el1->el_next; in equiv_enum()
320 if (el1 || el2) in equiv_enum()
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| /freebsd/sys/contrib/device-tree/src/arm64/qcom/ |
| H A D | x1-el2.dtso | 21 * can't use MSI on some PCIe controllers in EL1. But we can add them
|
| /freebsd/sys/arm64/include/ |
| H A D | pte.h | 69 #define ATTR_S2_XN_NONE 0UL /* Allow execution at EL0 & EL1 */
72 #define ATTR_S2_XN_EL0 3UL /* Allow execution at EL1 */
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| /freebsd/contrib/ntp/include/ |
| H A D | ntp_prio_q.h | 53 int get_fifo_order(const void *el1, const void *el2);
|
| /freebsd/sys/contrib/device-tree/Bindings/firmware/ |
| H A D | intel,stratix10-svc.txt | 16 (EL1, Exception Layer 1), interfaces with the service providers and provides
|
| H A D | intel,stratix10-svc.yaml | 27 (EL1, Exception Layer 1), interfaces with the service providers and provides
|
| /freebsd/sys/arm64/spe/ |
| H A D | arm_spe.h | 59 /* Profile kernel (EL1), userspace (EL0) or both */
|
| /freebsd/sys/arm64/vmm/io/ |
| H A D | vtimer.c | 161 * CNTHCTL_E2H_EL1PCEN: trap EL1 access to in vtimer_vminit()
185 * from EL1 in vtimer_vminit()
|
| /freebsd/contrib/ntp/ntpd/ |
| H A D | ntp_prio_q.c | 235 int get_fifo_order(const void *el1, const void *el2) in get_fifo_order() argument
|
| /freebsd/contrib/llvm-project/lldb/source/Plugins/Instruction/ARM64/ |
| H A D | EmulateInstructionARM64.h | 91 enum ExceptionLevel { EL0 = 0, EL1 = 1, EL2 = 2, EL3 = 3 }; enumerator
|
| /freebsd/contrib/ncurses/ncurses/tinfo/ |
| H A D | lib_win32con.c | 710 rkeycompare(const void *el1, const void *el2) in rkeycompare() argument
712 WORD key1 = (LOWORD((*((const LONG *) el1)))) & 0x7fff; in rkeycompare()
719 keycompare(const void *el1, const void *el2) in keycompare() argument
721 WORD key1 = HIWORD((*((const LONG *) el1))); in keycompare()
|
| /freebsd/sys/dev/hwpmc/ |
| H A D | hwpmc_arm64.c | 194 /* If in VHE we need to include EL2 and exclude EL1 */ in arm64_allocate_pmc()
199 /* Exclude EL1 */ in arm64_allocate_pmc()
|
| /freebsd/contrib/llvm-project/clang/lib/Driver/ToolChains/Arch/ |
| H A D | AArch64.cpp | 265 else if (Mtp == "el1" || Mtp == "tpidr_el1") in getAArch64TargetFeatures()
266 Features.push_back("+tpidr-el1"); in getAArch64TargetFeatures()
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| /freebsd/contrib/opencsd/decoder/include/opencsd/ |
| H A D | ocsd_if_types.h | 353 ocsd_EL1, /**< EL1 */
434 OCSD_MEM_SPACE_EL1S = 0x1, /**< S EL1/0 */
435 OCSD_MEM_SPACE_EL1N = 0x2, /**< NS EL1/0 */
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| /freebsd/lib/libpmc/pmu-events/arch/arm64/ |
| H A D | common-and-microarch.json | 411 "PublicDescription": "PMU overflow, counters accessible to EL1 and EL0",
414 "BriefDescription": "PMU overflow, counters accessible to EL1 and EL0"
|