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/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a55/
H A D	pipeline.json	9 …"PublicDescription": "No operation issued due to the frontend, cache miss.This event counts every … 12 …"BriefDescription": "No operation issued due to the frontend, cache miss.This event counts every c… 15 …"PublicDescription": "No operation issued due to the frontend, TLB miss.This event counts every cy… 18 …"BriefDescription": "No operation issued due to the frontend, TLB miss.This event counts every cyc… 21 …"PublicDescription": "No operation issued due to the frontend, pre-decode error.This event counts … 24 …"BriefDescription": "No operation issued due to the frontend, pre-decode error.This event counts e… 27 …ration issued due to the backend interlock.This event counts every cycle that issue is stalled and… 30 …ration issued due to the backend interlock.This event counts every cycle that issue is stalled and… 33 …due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there i… 36 …due to the backend, interlock, AGU.This event counts every cycle that issue is stalled and there i… [all …]
H A D	branch.json	18 …tor is retired. This event still counts when branch prediction is disabled due to the MMU being of… 21 …tor is retired. This event still counts when branch prediction is disabled due to the MMU being of… 24 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 27 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 30 …due to address mis-compare.This event counts when any indirect branch which can be predicted by th… 33 …due to address mis-compare.This event counts when any indirect branch which can be predicted by th… 36 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 39 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 42 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 45 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… [all …]
/linux/tools/perf/pmu-events/arch/arm64/arm/cortex-a510/
H A D	pipeline.json	21 …"PublicDescription": "No operation issued due to the frontend, cache miss. This event counts every… 24 …"BriefDescription": "No operation issued due to the frontend, cache miss. This event counts every … 27 …"PublicDescription": "No operation issued due to the frontend, TLB miss. This event counts every c… 30 …"BriefDescription": "No operation issued due to the frontend, TLB miss. This event counts every cy… 33 "PublicDescription": "No operation issued due to the frontend, pre-decode error", 36 "BriefDescription": "No operation issued due to the frontend, pre-decode error" 39 …ed due to the backend interlock. This event counts every cycle where the issue of an operation is … 42 …ed due to the backend interlock. This event counts every cycle where the issue of an operation is … 45 …due to the backend, address interlock. This event counts every cycle where the issue of an operati… 48 …due to the backend, address interlock. This event counts every cycle where the issue of an operati… [all …]
H A D	branch.json	18 …ict is retired. This event still counts when branch prediction is disabled due to the Memory Manag… 21 …ict is retired. This event still counts when branch prediction is disabled due to the Memory Manag… 24 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 27 …or the address. This event still counts when branch prediction is disabled due to the MMU being of… 30 …due to address miscompare. This event counts when any indirect branch that the BTAC can predict is… 33 …due to address miscompare. This event counts when any indirect branch that the BTAC can predict is… 36 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 39 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 42 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… 45 … the condition. This event still counts when branch prediction is disabled due to the MMU being of… [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power10/
H A D	datasource.json	15 …cessor's L1 data cache was reloaded from a source beyond the local core's L2 due to a demand miss." 20 … "The processor's L1 data cache was reloaded from beyond the local core's L3 due to a demand miss." 30 …he processor's data cache was reloaded from local, remote, or distant memory due to a demand miss." 60 …n": "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss." 65 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a … 70 …: "The processor's instruction cache was reloaded from the local core's L2 due to a demand miss or… 75 …"BriefDescription": "The processor's L1 data cache was reloaded from the local core's L2 due to a … 80 …or's instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss." 85 …cessor's L1 data cache was reloaded from a source beyond the local core's L1 due to a demand miss." 90 …'s instruction cache was reloaded from a source beyond the local core's L1 due to a demand miss or… [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power8/
H A D	cache.json	5 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 6 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema… 11 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a demand load", 12 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either only dema… 17 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a demand load", 18 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either only dema… 23 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a demand … 24 …"PublicDescription": "The processor's data cache was reloaded from local core's L2 due to either o… 35 …sor's data cache was reloaded from a location other than the local core's L2 due to a demand load", 36 …r's data cache was reloaded from a location other than the local core's L2 due to either only dema… [all …]
H A D	frontend.json	89 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f… 90 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru… 95 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to an instruction f… 96 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to either an instru… 101 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to an instruction f… 102 …was reloaded from another chip's L4 on a different Node or Group (Distant) due to either an instru… 107 …as reloaded from another chip's memory on the same Node or Group (Distant) due to an instruction f… 108 …as reloaded from another chip's memory on the same Node or Group (Distant) due to either an instru… 113 …"BriefDescription": "The processor's Instruction cache was reloaded from local core's L2 due to an… 114 …"PublicDescription": "The processor's Instruction cache was reloaded from local core's L2 due to e… [all …]
H A D	marked.json	35 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 41 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 47 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 53 …another chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a marked load", 59 …e was reloaded from another chip's L4 on a different Node or Group (Distant) due to a marked load", 65 …cles to reload from another chip's L4 on a different Node or Group (Distant) due to a marked load", 71 … was reloaded from another chip's memory on the same Node or Group (Distant) due to a marked load", 77 …les to reload from another chip's memory on the same Node or Group (Distant) due to a marked load", 83 …"BriefDescription": "The processor's data cache was reloaded from local core's L2 due to a marked … 95 …"Duration in cycles to reload from a location other than the local core's L2 due to a marked load", [all …]
H A D	other.json	77 …"BriefDescription": "Read blocked due to interleave conflict. The ifar logic will detect an interl… 95 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Count Cache Tar… 101 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the BHT Direction P… 107 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Link Stack Targ… 113 …"BriefDescription": "Conditional Branch Completed that was Mispredicted due to the Target Address … 251 "BriefDescription": "Completion stall due to IFU", 257 "BriefDescription": "Completion stall due to CO q full", 263 "BriefDescription": "completion stall due to flush by own thread", 269 "BriefDescription": "Completion stall due to mem ECC delay", 275 "BriefDescription": "Completion stall due to nop", [all …]
H A D	translation.json	29 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 35 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 41 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L2 due to a data… 47 …try was loaded into the TLB from a location other than the local core's L2 due to a data side requ… 53 …the TLB from local core's L2 hit without dispatch conflicts on Mepf state. due to a data side requ… 59 … Table Entry was loaded into the TLB from local core's L2 without conflict due to a data side requ… 65 …"BriefDescription": "A Page Table Entry was loaded into the TLB from local core's L3 due to a data… 71 … Entry was loaded into the TLB from local core's L3 with dispatch conflict due to a data side requ… 77 …the TLB from local core's L3 without dispatch conflicts hit on Mepf state. due to a data side requ… 83 … Table Entry was loaded into the TLB from local core's L3 without conflict due to a data side requ… [all …]
H A D	pipeline.json	29 "BriefDescription": "Completion stall due to a Branch Unit", 53 …"BriefDescription": "Completion stall due to cache miss that resolves in the L2 or L3 with a confl… 54 …"PublicDescription": "Completion stall due to cache miss resolving in core's L2/L3 with a conflict" 59 "BriefDescription": "Completion stall due to cache miss resolving missed the L3", 65 "BriefDescription": "Completion stall due to cache miss that resolves in local memory", 66 "PublicDescription": "Completion stall due to cache miss resolving in core's Local Memory" 77 "BriefDescription": "Completion stall due to LSU reject ERAT miss", 83 "BriefDescription": "Completion stall due to a long latency fixed point instruction", 89 "BriefDescription": "Completion stall due to FXU", 95 "BriefDescription": "completion stall due to hwsync", [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen3/
H A D	other.json	22 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 28 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 34 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 40 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 58 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 64 …ot get dispatched due to a Token Stall. Also counts cycles when the thread is not selected to disp… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]
/linux/tools/perf/pmu-events/arch/x86/alderlaken/
H A D	adln-metrics.json	88 …": "Counts the number of issue slots that were not consumed by the backend due to certain allocati… 96 …ounts the total number of issue slots that were not consumed by the backend due to backend stalls", 103 …unts the total number of issue slots that were not consumed by the backend due to backend stalls. … 107 … slots that were not consumed by the backend because allocation is stalled due to a mispredicted j… 114 … backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue s… 118 … "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which … 123 …due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was … 127 …": "Counts the number of issue slots that were not consumed by the backend due to branch mispredic… 136 … "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which … 144 … "Counts the number of issue slots that were not delivered by the frontend due to the microcode se… [all …]
/linux/tools/perf/pmu-events/arch/x86/grandridge/
H A D	grr-metrics.json	189 …": "Counts the number of issue slots that were not consumed by the backend due to certain allocati… 197 …ounts the total number of issue slots that were not consumed by the backend due to backend stalls", 203 …unts the total number of issue slots that were not consumed by the backend due to backend stalls. … 207 … slots that were not consumed by the backend because allocation is stalled due to a mispredicted j… 213 … backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue s… 217 … "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which … 222 …due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was … 226 …": "Counts the number of issue slots that were not consumed by the backend due to branch mispredic… 235 … "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which … 243 … "Counts the number of issue slots that were not delivered by the frontend due to the microcode se… [all …]
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 11 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.", 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 46 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor… 54 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa… 62 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or… 66 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… [all …]
/linux/tools/perf/pmu-events/arch/powerpc/power9/
H A D	translation.json	15 …che was reloaded with Shared (S) data from another core's L2 on the same chip due to a demand load" 25 …nto the TLB from another chip's memory on the same Node or Group (Distant) due to a data side requ… 35 …m another chip's L2 or L3 on the same Node or Group (Remote), as this chip due to a instruction si… 45 …"BriefDescription": "Finish stall due to a vector fixed point instruction in the execution pipelin… 60 …other chip's L2 or L3 on a different Node or Group (Distant), as this chip due to a data side requ… 65 …"BriefDescription": "Completion stall due to a long latency vector fixed point instruction (divisi… 70 …ssor's data cache was reloaded from a location other than the local core's L2 due to a demand load" 75 … either shared or modified data from another core's L2/L3 on the same chip due to a instruction si… 80 … was reloaded with Shared (S) data from another core's L2 on the same chip due to an instruction f… 95 …e was reloaded with Modified (M) data from another core's L2 on the same chip due to a demand load" [all …]
H A D	marked.json	20 … into the TLB with Shared (S) data from another core's L3 on the same chip due to a data side requ… 25 …e was reloaded from another chip's memory on the same Node or Group ( Remote) due to a demand load" 35 …Instruction cache was reloaded from local core's L2 with dispatch conflict due to an instruction f… 55 "BriefDescription": "Completion stall due to ntc flush" 60 …"A Page Table Entry was loaded into the TLB from the local chip's L4 cache due to a marked data si… 70 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a marked data si… 80 …sor's Instruction cache was reloaded from local core's L2 without conflict due to an instruction f… 85 …truction cache was reloaded from a location other than the local core's L3 due to a instruction fe… 95 …the TLB with Modified (M) data from another core's ECO L3 on the same chip due to a marked data si… 100 …o the TLB with Shared (S) data from another core's ECO L3 on the same chip due to a data side requ… [all …]
/linux/tools/perf/pmu-events/arch/x86/goldmontplus/
H A D	virtual-memory.json	3 "BriefDescription": "Page walk completed due to a demand load to a 1GB page", 7 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 12 "BriefDescription": "Page walk completed due to a demand load to a 2M or 4M page", 16 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 21 "BriefDescription": "Page walk completed due to a demand load to a 4K page", 25 …"PublicDescription": "Counts page walks completed due to demand data loads (including SW prefetche… 30 "BriefDescription": "Page walks outstanding due to a demand load every cycle.", 34 …"PublicDescription": "Counts once per cycle for each page walk occurring due to a load (demand dat… 39 "BriefDescription": "Page walk completed due to a demand data store to a 1GB page", 43 …"PublicDescription": "Counts page walks completed due to demand data stores whose address translat… [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereonex/
H A D	core-imp-def.json	93 … "PublicDescription": "Count predict pipe stalls due to speculative return address predictor full", 96 … "BriefDescription": "Count predict pipe stalls due to speculative return address predictor full" 111 "PublicDescription": "Flushes due to memory hazards", 114 "BriefDescription": "Flushes due to memory hazards" 201 "PublicDescription": "Stall due to BOB ID", 204 "BriefDescription": "Stall due to BOB ID" 207 "PublicDescription": "Dispatch stall due to LOB entries", 210 "BriefDescription": "Dispatch stall due to LOB entries" 213 "PublicDescription": "Dispatch stall due to SOB entries", 216 "BriefDescription": "Dispatch stall due to SOB entries" [all …]
/linux/tools/perf/pmu-events/arch/x86/sierraforest/
H A D	srf-metrics.json	261 …": "Counts the number of issue slots that were not consumed by the backend due to certain allocati… 269 …ounts the total number of issue slots that were not consumed by the backend due to backend stalls", 275 …unts the total number of issue slots that were not consumed by the backend due to backend stalls. … 279 … slots that were not consumed by the backend because allocation is stalled due to a mispredicted j… 285 … backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue s… 289 … "Counts the number of issue slots that were not delivered by the frontend due to BACLEARS, which … 294 …due to BACLEARS, which occurs when the Branch Target Buffer (BTB) prediction or lack thereof, was … 298 …": "Counts the number of issue slots that were not consumed by the backend due to branch mispredic… 307 … "Counts the number of issue slots that were not delivered by the frontend due to BTCLEARS, which … 315 … "Counts the number of issue slots that were not delivered by the frontend due to the microcode se… [all …]
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 11 "BriefDescription": "Counts the number of page walks completed due to load DTLB misses.", 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 46 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to stor… 54 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 1G pa… 62 …"BriefDescription": "Counts the number of page walks completed due to store DTLB misses to a 2M or… 66 …"PublicDescription": "Counts the number of page walks completed due to stores whose address transl… [all …]
/linux/tools/perf/pmu-events/arch/arm64/ampere/ampereone/
H A D	core-imp-def.json	93 … "PublicDescription": "Count predict pipe stalls due to speculative return address predictor full", 96 … "BriefDescription": "Count predict pipe stalls due to speculative return address predictor full" 111 "PublicDescription": "Flushes due to memory hazards", 114 "BriefDescription": "Flushes due to memory hazards" 201 "PublicDescription": "Stall due to BOB ID", 204 "BriefDescription": "Stall due to BOB ID" 207 "PublicDescription": "Dispatch stall due to LOB entries", 210 "BriefDescription": "Dispatch stall due to LOB entries" 213 "PublicDescription": "Dispatch stall due to SOB entries", 216 "BriefDescription": "Dispatch stall due to SOB entries" [all …]
/linux/tools/perf/pmu-events/arch/x86/snowridgex/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 11 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 41 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 50 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… [all …]
/linux/tools/perf/pmu-events/arch/x86/elkhartlake/
H A D	virtual-memory.json	3 …"BriefDescription": "Counts the number of page walks due to loads that miss the PDE (Page Director… 11 …"BriefDescription": "Counts the number of first level TLB misses but second level hits due to a de… 19 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page… 23 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 28 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 1G pag… 32 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 37 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 2M or … 41 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… 46 …"BriefDescription": "Counts the number of page walks completed due to load DTLB misses to a 4K pag… 50 …"PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetc… [all …]
/linux/tools/perf/pmu-events/arch/x86/amdzen2/
H A D	other.json	28 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 34 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 40 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 46 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 52 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 58 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 64 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 70 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 76 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… 82 …"BriefDescription": "Cycles where a dispatch group is valid but does not get dispatched due to a t… [all …]

12 3 4 5 6 7 8 9 10 >>...133