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/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dqcom,dispcc-sc8280xp.yaml30 - description: DisplayPort 0 link clock
31 - description: DisplayPort 0 VCO div clock
32 - description: DisplayPort 1 link clock
33 - description: DisplayPort 1 VCO div clock
34 - description: DisplayPort 2 link clock
35 - description: DisplayPort 2 VCO div clock
36 - description: DisplayPort 3 link clock
37 - description: DisplayPort 3 VCO div clock
H A Dqcom,glymur-dispcc.yaml28 - description: DisplayPort 0 link clock
29 - description: DisplayPort 0 VCO div clock
30 - description: DisplayPort 1 link clock
31 - description: DisplayPort 1 VCO div clock
32 - description: DisplayPort 2 link clock
33 - description: DisplayPort 2 VCO div clock
34 - description: DisplayPort 3 link clock
35 - description: DisplayPort 3 VCO div clock
H A Dqcom,mmcc.yaml282 - description: DisplayPort phy PLL link clock
283 - description: DisplayPort phy PLL vco clock
318 - description: DisplayPort phy PLL link clock
319 - description: DisplayPort phy PLL vco clock
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dapple,atcphy.yaml14 USB4/Thunderbolt, and DisplayPort connectivity via Type-C ports found in
21 pairs as distinct DisplayPort lanes. Any reference to lane in this binding
61 - description: Common controls for all PHYs (USB2/3/4, DisplayPort, TBT)
62 - description: DisplayPort Alternate Mode PHY specific controls
100 description: Incoming endpoint from the DisplayPort controller.
141 DisplayPort tunables for lane 0.
143 Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
144 and not to an individual DisplayPort differential lane.
149 DisplayPort tunables for lane 1.
151 Note that lane here refers to a USB RX and TX pair re-used for DisplayPort
[all …]
H A Dgoogle,lga-usb-phy.yaml17 and USB3.2/DisplayPort combo PHY IP.
25 - description: USB3.2/DisplayPort combo PHY core registers.
26 - description: USB3.2/DisplayPort combo PHY Type-C Assist registers.
43 - 2 for DisplayPort.
50 - description: USB3.2/DisplayPort combo PHY clock.
51 - description: USB3.2/DisplayPort combo PHY firmware clock.
64 - description: USB3.2/DisplayPort combo PHY reset.
H A Dqcom,sc8280xp-qmp-usb43dp-phy.yaml115 - items: # DisplayPort 1 lane, normal orientation
117 - items: # DisplayPort 1 lane, flipped orientation
119 - items: # DisplayPort 2 lanes, normal orientation
122 - items: # DisplayPort 2 lanes, flipped orientation
125 - items: # DisplayPort 4 lanes, normal orientation
130 - items: # DisplayPort 4 lanes, flipped orientation
167 description: Incoming endpoint from the DisplayPort controller
H A Dqcom,qcs615-qmp-usb3dp-phy.yaml14 and DisplayPort over USB-C. While it enables mode switching between USB3 and
15 DisplayPort, but does not support combo mode.
H A Dphy-rockchip-usbdp.yaml61 determines the DisplayPort (DP) lane index, while the value of an entry
68 DP lanes are mapped by DisplayPort Alt mode, this property is not needed.
H A Dphy-cadence-torrent.yaml11 hardware included with the Cadence MHDP DisplayPort controller. Torrent
122 Maximum DisplayPort link bit rate to use, in Mbps
H A Dsamsung,dp-video-phy.yaml7 title: Samsung Exynos SoC DisplayPort PHY
/freebsd/sys/contrib/device-tree/Bindings/display/xlnx/
H A Dxlnx,zynqmp-dpsub.yaml7 title: Xilinx ZynqMP DisplayPort Subsystem
10 The DisplayPort subsystem of Xilinx ZynqMP (Zynq UltraScale+ MPSoC)
11 implements the display and audio pipelines based on the DisplayPort v1.2
18 | 2x aud | | | Audio/Video | --> | Pipeline | | | DisplayPort |---> | PHY0 |
33 conversion. The Audio Mixer mixes the incoming audio streams. The DisplayPort
34 Source Controller handles the DisplayPort protocol and connects to external
127 Connections to the programmable logic and the DisplayPort PHYs. Each port
153 description: The DisplayPort output
/freebsd/sys/contrib/device-tree/Bindings/display/tegra/
H A Dnvidia,tegra124-dpaux.yaml7 title: NVIDIA Tegra DisplayPort AUX Interface
18 When configured for DisplayPort AUX operation, the DPAUX controller
19 can also be used to communicate with a DisplayPort device using the
76 description: phandle of a supply that powers the DisplayPort
/freebsd/sys/contrib/device-tree/Bindings/display/rockchip/
H A Drockchip,dw-dp.yaml7 title: Rockchip DW DisplayPort Transmitter
14 which is compliant with the DisplayPort Specification Version 1.4 with the
17 * DisplayPort 1.4a
46 - description: DisplayPort AUX clock
/freebsd/sys/contrib/device-tree/Bindings/display/
H A Ddp-aux-bus.yaml7 title: DisplayPort AUX bus
13 DisplayPort controllers provide a control channel to the sinks that
/freebsd/sys/contrib/device-tree/Bindings/dma/xilinx/
H A Dxlnx,zynqmp-dpdma.yaml7 title: Xilinx ZynqMP DisplayPort DMA Controller
11 DisplayPort Subsystem. The DMA engine supports up to 6 DMA channels (3
/freebsd/sys/contrib/device-tree/Bindings/display/bridge/
H A Dparade,ps8622.yaml7 title: Parade PS8622/PS8625 DisplayPort to LVDS Converter
50 description: Video port for DisplayPort input.
H A Dite,it6505.yaml16 The IT6505 is a high-performance DisplayPort 1.1a transmitter,
17 fully compliant with DisplayPort 1.1a, HDCP 1.3 specifications.
/freebsd/sys/dev/drm2/
H A Ddrm_dp_helper.h33 * eDP: Embedded DisplayPort version 1
34 * DPI: DisplayPort Interoperability Guideline v1.1a
35 * 1.2: DisplayPort 1.2
76 /* 00b = DisplayPort */
/freebsd/sys/contrib/device-tree/Bindings/display/mediatek/
H A Dmediatek,dpi.yaml87 attached HDMI, LVDS or DisplayPort encoder chip.
99 description: DPI output to an HDMI, LVDS or DisplayPort encoder input
/freebsd/sys/contrib/device-tree/Bindings/display/msm/
H A Ddp-controller.yaml14 Device tree bindings for DisplayPort host controller for MSM targets
15 that are compatible with VESA DisplayPort interface specification.
359 displayport-controller@ae90000 {
H A Dqcom,x1e80100-mdss.yaml45 "^displayport-controller@[0-9a-f]+$":
171 displayport-controller@ae90000 {
H A Dqcom,glymur-mdss.yaml49 "^displayport-controller@[0-9a-f]+$":
179 displayport-controller@af54000 {
H A Dqcom,sc7180-mdss.yaml57 "^displayport-controller@[0-9a-f]+$":
251 displayport-controller@ae90000 {
/freebsd/sys/contrib/device-tree/Bindings/connector/
H A Dusb-connector.yaml166 "^(displayport)$":
424 # to companion PMIC (max77865), SS lines to USB3 PHY and SBU to DisplayPort.
425 # DisplayPort video lines are routed to the connector via SS mux in USB3 PHY.
433 displayport {
/freebsd/sys/contrib/device-tree/Bindings/sound/
H A Drockchip,rk3399-gru-sound.yaml27 DisplayPort audio codec is referenced in rockchip,codec

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