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/linux/Documentation/devicetree/bindings/usb/
H A Dqcom,snps-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/qcom,snps-dwc3.yaml#
7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
13 Describes the Qualcomm USB block, based on Synopsys DWC3.
19 const: qcom,snps-dwc3
27 - qcom,glymur-dwc3
28 - qcom,glymur-dwc3-mp
29 - qcom,ipq4019-dwc3
30 - qcom,ipq5018-dwc3
31 - qcom,ipq5332-dwc3
32 - qcom,ipq5424-dwc3
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H A Dqcom,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
7 title: Legacy Qualcomm SuperSpeed DWC3 USB SoC controller
12 # Use the combined qcom,snps-dwc3 instead
19 const: qcom,dwc3
27 - qcom,ipq4019-dwc3
28 - qcom,ipq5018-dwc3
29 - qcom,ipq5332-dwc3
30 - qcom,ipq5424-dwc3
31 - qcom,ipq6018-dwc3
32 - qcom,ipq8064-dwc3
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H A Drockchip,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/rockchip,dwc3.yaml#
7 title: Rockchip SuperSpeed DWC3 USB SoC controller
13 The common content of the node is defined in snps,dwc3.yaml.
28 - rockchip,rk3328-dwc3
29 - rockchip,rk3562-dwc3
30 - rockchip,rk3568-dwc3
31 - rockchip,rk3576-dwc3
32 - rockchip,rk3588-dwc3
40 - rockchip,rk3328-dwc3
41 - rockchip,rk3562-dwc3
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H A Dapple,dwc3.yaml4 $id: http://devicetree.org/schemas/usb/apple,dwc3.yaml#
7 title: Apple Silicon DWC3 USB controller
13 Apple Silicon SoCs use a Synopsys DesignWare DWC3 based controller for each of
17 - $ref: snps,dwc3-common.yaml#
24 - apple,t6000-dwc3
25 - apple,t6020-dwc3
26 - apple,t8112-dwc3
27 - const: apple,t8103-dwc3
28 - const: apple,t8103-dwc3
32 - description: Core DWC3 region
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H A Drealtek,rtd-dwc3.yaml5 $id: http://devicetree.org/schemas/usb/realtek,rtd-dwc3.yaml#
8 title: Realtek DWC3 USB SoC Controller Glue
14 The Realtek DHC SoC embeds a DWC3 USB IP Core configured for USB 2.0
21 - realtek,rtd1295-dwc3
22 - realtek,rtd1315e-dwc3
23 - realtek,rtd1319-dwc3
24 - realtek,rtd1319d-dwc3
25 - realtek,rtd1395-dwc3
26 - realtek,rtd1619-dwc3
27 - realtek,rtd1619b-dwc3
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H A Ddwc3-st.txt1 ST DWC3 glue logic
3 This file documents the parameters for the dwc3-st driver.
4 This driver controls the glue logic used to configure the dwc3 core on
8 - compatible : must be "st,stih407-dwc3"
32 The dwc3 core should be added as subnode to ST DWC3 glue as shown in the
33 example below. The DT binding details of dwc3 can be found in:
34 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
37 is "otg", which isn't supported by this SoC. Valid dr_mode values for dwc3-st are either "host"
44 st_dwc3: dwc3@8f94000 {
45 compatible = "st,stih407-dwc3";
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H A Dfsl,ls1028a.yaml7 title: Freescale layerscape SuperSpeed DWC3 USB SoC controller
17 - fsl,ls1012a-dwc3
18 - fsl,ls1043a-dwc3
19 - fsl,ls1046a-dwc3
20 - fsl,ls1088a-dwc3
21 - fsl,ls208xa-dwc3
22 - fsl,lx2160a-dwc3
23 - const: fsl,ls1028a-dwc3
24 - const: fsl,ls1028a-dwc3
45 - $ref: snps,dwc3-common.yaml#
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H A Domap-usb.txt46 OMAP DWC3 GLUE
48 * "ti,dwc3" for OMAP5 and DRA7
49 * "ti,am437x-dwc3" for AM437x
60 - extcon : phandle for the extcon device omap dwc3 uses to detect
65 The dwc3 core should be added as subnode to omap dwc3 glue.
66 - dwc3 :
67 The binding details of dwc3 can be found in:
68 Documentation/devicetree/bindings/usb/snps,dwc3.yaml
71 compatible = "ti,dwc3";
H A Dfsl,imx8mq-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/fsl,imx8mq-dwc3.yaml#
18 - fsl,imx8mq-dwc3
25 - const: fsl,imx8mq-dwc3
26 - const: snps,dwc3
29 - $ref: snps,dwc3.yaml#
39 compatible = "fsl,imx8mq-dwc3", "snps,dwc3";
H A Dfsl,imx8mp-dwc3.yaml5 $id: http://devicetree.org/schemas/usb/fsl,imx8mp-dwc3.yaml#
17 - const: fsl,imx95-dwc3
18 - const: fsl,imx8mp-dwc3
19 - const: fsl,imx8mp-dwc3
24 - description: Address and length of the register set for the wrapper of dwc3 core on the SOC.
85 $ref: snps,dwc3.yaml#
102 const: fsl,imx8mp-dwc3
115 compatible = "fsl,imx8mp-dwc3";
129 compatible = "snps,dwc3";
H A Dti,keystone-dwc3.yaml4 $id: http://devicetree.org/schemas/usb/ti,keystone-dwc3.yaml#
16 - ti,keystone-dwc3
17 - ti,am654-dwc3
61 $ref: snps,dwc3.yaml#
77 dwc3@2680000 {
78 compatible = "ti,keystone-dwc3";
87 compatible = "snps,dwc3";
H A Ddwc3-xilinx.yaml4 $id: http://devicetree.org/schemas/usb/dwc3-xilinx.yaml#
7 title: Xilinx SuperSpeed DWC3 USB SoC controller
16 - xlnx,zynqmp-dwc3
17 - xlnx,versal-dwc3
86 $ref: snps,dwc3.yaml#
106 - xlnx,versal-dwc3
136 compatible = "xlnx,zynqmp-dwc3";
150 compatible = "snps,dwc3";
/linux/drivers/usb/dwc3/
H A Dglue.h13 * dwc3_properties: DWC3 core properties
26 * @dwc: Reference to dwc3 context structure
27 * @res: resource for the DWC3 core mmio region
29 * be ignored by the DWC3 core, as they are managed by the glue
32 * @properties: dwc3 software manage properties
35 struct dwc3 *dwc;
43 * dwc3_core_probe - Initialize the core dwc3 driver
57 * dwc3_core_remove - Deinitialize and remove the core dwc3 driver
58 * @dwc: Pointer to DWC3 controller context
60 * Cleans up resources and disables the dwc3 core driver. This should be called
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H A DMakefile5 obj-$(CONFIG_USB_DWC3) += dwc3.o
7 dwc3-y := core.o
10 dwc3-y += trace.o
14 dwc3-y += host.o
18 dwc3-y += gadget.o ep0.o
22 dwc3-y += drd.o
26 dwc3-y += ulpi.o
30 dwc3-y += debugfs.o
45 obj-$(CONFIG_USB_DWC3_AM62) += dwc3-am62.o
46 obj-$(CONFIG_USB_DWC3_APPLE) += dwc3-apple.o
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H A Ddwc3-haps.c3 * dwc3-haps.c - Synopsys HAPS PCI Specific glue layer
20 * @dwc3: child dwc3 platform_device
24 struct platform_device *dwc3; member
60 dwc->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO); in dwc3_haps_probe()
61 if (!dwc->dwc3) in dwc3_haps_probe()
75 ret = platform_device_add_resources(dwc->dwc3, res, ARRAY_SIZE(res)); in dwc3_haps_probe()
77 dev_err(dev, "couldn't add resources to dwc3 device\n"); in dwc3_haps_probe()
82 dwc->dwc3->dev.parent = dev; in dwc3_haps_probe()
84 ret = device_add_software_node(&dwc->dwc3->dev, &dwc3_haps_swnode); in dwc3_haps_probe()
88 ret = platform_device_add(dwc->dwc3); in dwc3_haps_probe()
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H A Ddwc3-apple.c3 * Apple Silicon DWC3 Glue driver
7 * - dwc3-qcom.c Copyright (c) 2018, The Linux Foundation. All rights reserved.
8 * - dwc3-of-simple.c Copyright (c) 2015 Texas Instruments Incorporated - https://www.ti.com
20 * This platform requires a very specific sequence of operations to bring up dwc3 and its USB3 PHY:
24 * 2) DWC3 has to be brought up but we must not touch the gadget area or start xhci yet.
25 * 3) The PHY bring-up has to be finalized and dwc3's PIPE interface has to be switched to the
33 * 1) DWC3 has to exit host or gadget mode and must no longer touch those registers
34 * 2) The PHY has to switch dwc3's PIPE interface back to the dummy backend
37 * We also can't transition the PHY from one mode to another while dwc3 is up and running (this is
41 * After both the PHY and dwc3 are initialized we will only ever see a single "new device connected"
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H A Ddwc3-imx8mp.c3 * dwc3-imx8mp.c - NXP imx8mp Specific Glue layer
54 struct platform_device *dwc3; member
103 struct dwc3 *dwc3 = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_wakeup_enable() local
106 if (!dwc3) in dwc3_imx8mp_wakeup_enable()
111 if ((dwc3->current_dr_role == DWC3_GCTL_PRTCAP_HOST) && dwc3->xhci) { in dwc3_imx8mp_wakeup_enable()
145 struct dwc3 *dwc = platform_get_drvdata(dwc3_imx->dwc3); in dwc3_imx8mp_interrupt()
211 "snps,dwc3"); in dwc3_imx8mp_probe()
213 return dev_err_probe(dev, -ENODEV, "failed to find dwc3 core child\n"); in dwc3_imx8mp_probe()
232 dev_err(&pdev->dev, "failed to create dwc3 core\n"); in dwc3_imx8mp_probe()
236 dwc3_imx->dwc3 = of_find_device_by_node(dwc3_np); in dwc3_imx8mp_probe()
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H A DKconfig14 module, the module will be called dwc3.ko.
22 Select this if you have ULPI type PHY attached to your DWC3
26 prompt "DWC3 Mode Selection"
35 Select this when you want to use DWC3 in host mode only,
42 Select this when you want to use DWC3 in gadget mode only,
49 This is the default mode of working of DWC3 controller where
182 tristate "Realtek DWC3 Platform Driver"
193 tristate "DWC3 Generic Platform Driver"
199 dwc3-of-simple can easily switch to dwc3-generic by flattening
200 the dwc3 child node in the device tree.
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H A Ddwc3-pci.c3 * dwc3-pci.c - PCI Specific glue layer
76 * @dwc3: child dwc3 platform_device
83 struct platform_device *dwc3; member
285 * Make the pdev name predictable (only 1 DWC3 on BYT) in dwc3_pci_quirks()
289 dwc->dwc3->id = PLATFORM_DEVID_NONE; in dwc3_pci_quirks()
290 platform_bytcr_gpios.dev_id = "dwc3.ulpi"; in dwc3_pci_quirks()
310 return device_add_software_node(&dwc->dwc3->dev, swnode); in dwc3_pci_quirks()
317 struct platform_device *dwc3 = dwc->dwc3; in dwc3_pci_resume_work() local
320 ret = pm_runtime_get_sync(&dwc3->dev); in dwc3_pci_resume_work()
322 pm_runtime_put_sync_autosuspend(&dwc3->dev); in dwc3_pci_resume_work()
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H A Dcore.c53 static int dwc3_get_dr_mode(struct dwc3 *dwc) in dwc3_get_dr_mode()
96 !DWC3_VER_IS_PRIOR(DWC3, 330A)) in dwc3_get_dr_mode()
111 void dwc3_enable_susphy(struct dwc3 *dwc, bool enable) in dwc3_enable_susphy()
138 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode, bool ignore_susphy) in dwc3_set_prtcap()
167 struct dwc3 *dwc = work_to_dwc(work); in __dwc3_set_mode()
216 if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) || in __dwc3_set_mode()
290 void dwc3_set_mode(struct dwc3 *dwc, u32 mode) in dwc3_set_mode()
306 struct dwc3 *dwc = dep->dwc; in dwc3_core_fifo_space()
322 int dwc3_core_soft_reset(struct dwc3 *dwc) in dwc3_core_soft_reset()
329 * XHCI driver will reset the host block. If dwc3 was configured for in dwc3_core_soft_reset()
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H A Ddrd.c19 static void dwc3_otg_disable_events(struct dwc3 *dwc, u32 disable_mask) in dwc3_otg_disable_events()
27 static void dwc3_otg_enable_events(struct dwc3 *dwc, u32 enable_mask) in dwc3_otg_enable_events()
35 static void dwc3_otg_clear_events(struct dwc3 *dwc) in dwc3_otg_clear_events()
54 struct dwc3 *dwc = _dwc; in dwc3_otg_thread_irq()
72 struct dwc3 *dwc = _dwc; in dwc3_otg_irq()
93 static void dwc3_otgregs_init(struct dwc3 *dwc) in dwc3_otgregs_init()
137 static int dwc3_otg_get_irq(struct dwc3 *dwc) in dwc3_otg_get_irq()
167 void dwc3_otg_init(struct dwc3 *dwc) in dwc3_otg_init()
186 void dwc3_otg_exit(struct dwc3 *dwc) in dwc3_otg_exit()
195 void dwc3_otg_host_init(struct dwc3 *dwc) in dwc3_otg_host_init()
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H A Dgadget.c41 int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) in dwc3_gadget_set_test_mode()
72 int dwc3_gadget_get_link_state(struct dwc3 *dwc) in dwc3_gadget_get_link_state()
89 int dwc3_gadget_set_link_state(struct dwc3 *dwc, enum dwc3_link_state state) in dwc3_gadget_set_link_state()
98 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) { in dwc3_gadget_set_link_state()
125 if (!DWC3_VER_IS_PRIOR(DWC3, 194A)) in dwc3_gadget_set_link_state()
142 static void dwc3_ep0_reset_state(struct dwc3 *dwc) in dwc3_ep0_reset_state()
196 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_del_and_unmap_request()
229 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_giveback()
255 int dwc3_send_gadget_generic_command(struct dwc3 *dwc, unsigned int cmd, in dwc3_send_gadget_generic_command()
316 struct dwc3 *dwc = dep->dwc; in dwc3_send_gadget_ep_cmd()
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H A Ddwc3-generic-plat.c3 * dwc3-generic-plat.c - DesignWare USB3 generic platform driver
7 * Inspired by dwc3-qcom.c and dwc3-of-simple.c
25 struct dwc3 dwc;
139 return dev_err_probe(dev, ret, "failed to register DWC3 Core\n"); in dwc3_generic_probe()
146 struct dwc3 *dwc = platform_get_drvdata(pdev); in dwc3_generic_remove()
153 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_generic_suspend()
168 struct dwc3 *dwc = dev_get_drvdata(dev); in dwc3_generic_resume()
214 { .compatible = "spacemit,k1-dwc3", },
215 { .compatible = "fsl,ls1028a-dwc3", &fsl_ls1028_dwc3},
216 { .compatible = "eswin,eic7700-dwc3", &eic7700_dwc3},
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H A Dep0.c30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
33 static int dwc3_ep0_delegate_req(struct dwc3 *dwc,
40 struct dwc3 *dwc; in dwc3_ep0_prepare_one_trb()
68 struct dwc3 *dwc; in dwc3_ep0_start_trans()
92 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_queue()
196 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_queue()
224 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc) in dwc3_ep0_stall_and_restart()
259 struct dwc3 *dwc = dep->dwc; in __dwc3_gadget_ep0_set_halt()
269 struct dwc3 *dwc = dep->dwc; in dwc3_gadget_ep0_set_halt()
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/linux/Documentation/devicetree/bindings/soc/socionext/
H A Dsocionext,uniphier-dwc3-glue.yaml4 $id: http://devicetree.org/schemas/soc/socionext/socionext,uniphier-dwc3-glue.yaml#
7 title: Socionext UniPhier SoC DWC3 USB3.0 glue layer
13 DWC3 USB3.0 glue layer implemented on Socionext UniPhier SoCs is
14 a sideband logic handling signals to DWC3 host controller inside
21 - socionext,uniphier-pro4-dwc3-glue
22 - socionext,uniphier-pro5-dwc3-glue
23 - socionext,uniphier-pxs2-dwc3-glue
24 - socionext,uniphier-ld20-dwc3-glue
25 - socionext,uniphier-pxs3-dwc3-glue
26 - socionext,uniphier-nx1-dwc3-glue
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