| /freebsd/sys/contrib/device-tree/Bindings/ata/ |
| H A D | rockchip,dwc-ahci.yaml | 4 $id: http://devicetree.org/schemas/ata/rockchip,dwc-ahci.yaml#
7 title: Synopsys DWC AHCI SATA controller for Rockchip devices
13 This document defines device tree bindings for the Synopsys DWC
22 - rockchip,rk3568-dwc-ahci
23 - rockchip,rk3588-dwc-ahci
31 - rockchip,rk3568-dwc-ahci
32 - rockchip,rk3588-dwc-ahci
33 - const: snps,dwc-ahci
42 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
62 - $ref: snps,dwc-ahci-common.yaml#
[all …]
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| H A D | snps,dwc-ahci.yaml | 4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci.yaml#
7 title: Synopsys DWC AHCI SATA controller
13 This document defines device tree bindings for the generic Synopsys DWC
20 - snps,dwc-ahci
26 - $ref: snps,dwc-ahci-common.yaml#
32 const: snps,dwc-ahci
38 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
55 compatible = "snps,dwc-ahci";
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| H A D | snps,dwc-ahci-common.yaml | 4 $id: http://devicetree.org/schemas/ata/snps,dwc-ahci-common.yaml#
7 title: Synopsys DWC AHCI SATA controller properties
13 This document defines device tree schema for the generic Synopsys DWC
30 Basic DWC AHCI SATA clock sources like application AXI/AHB BIU clock,
61 normally supported by the DWC AHCI SATA controller.
83 $ref: '#/$defs/dwc-ahci-port'
88 dwc-ahci-port:
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| H A D | baikal,bt1-ahci.yaml | 14 DWC AHCI SATA v4.10a IP-core.
17 - $ref: snps,dwc-ahci-common.yaml#
50 $ref: /schemas/ata/snps,dwc-ahci-common.yaml#/$defs/dwc-ahci-port
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| /freebsd/sys/contrib/device-tree/Bindings/net/ |
| H A D | snps,dwc-qos-ethernet.txt | 1 * Synopsys DWC Ethernet QoS IP version 4.10 driver (GMAC)
14 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10"
16 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10"
18 - "snps,dwc-qos-ethernet-4.10"
20 "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10". It is supported to be
72 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
78 - "axis,artpec6-eqos", "snps,dwc-qos-ethernet-4.10":
83 - "snps,dwc-qos-ethernet-4.10" (deprecated):
97 - "nvidia,tegra186-eqos", "snps,dwc-qos-ethernet-4.10":
99 - "axis,artpec6-eqos", "snps,dwc
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| /freebsd/sys/contrib/device-tree/Bindings/display/bridge/ |
| H A D | dw_hdmi.txt | 5 TX Encoder (DWC HDMI TX). It doesn't constitue a device tree binding
13 - reg: Memory mapped base address and length of the DWC HDMI TX registers.
19 - interrupts: Reference to the DWC HDMI TX interrupt.
24 - clock-names: The DWC HDMI TX uses the following clocks.
30 - ports: The connectivity of the DWC HDMI TX with the rest of the system is
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| H A D | renesas,dw-hdmi.txt | 1 Renesas Gen3 DWC HDMI TX Encoder
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
33 - ports: See dw_hdmi.txt. The DWC HDMI shall have one port numbered 0
40 - power-domains: Shall reference the power domain that contains the DWC HDMI,
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| H A D | synopsys,dw-hdmi.yaml | 14 TX controller (DWC HDMI TX) IP core. It doesn't constitute a full device tree
16 bindings for the platform-specific integrations of the DWC HDMI TX.
53 functionally-reduced I2C master contained in the DWC HDMI. When connected
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| /freebsd/sys/contrib/device-tree/Bindings/ufs/ |
| H A D | tc-dwc-g210-pltfrm.txt | 11 "snps,dwc-ufshcd-1.40a"
19 Example for a setup using a 1.40a DWC Controller with a 6.00 G210 40-bit TC:
20 dwc-ufs@d0000000 {
22 "snps,dwc-ufshcd-1.40a",
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| H A D | snps,tc-dwc-g210.yaml | 4 $id: http://devicetree.org/schemas/ufs/snps,tc-dwc-g210.yaml#
18 - snps,dwc-ufshcd-1.40a
31 - const: snps,dwc-ufshcd-1.40a
47 "snps,dwc-ufshcd-1.40a",
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| /freebsd/sys/contrib/device-tree/Bindings/display/imx/ |
| H A D | hdmi.txt | 1 Freescale i.MX6 DWC HDMI TX Encoder
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
19 - ports: See dw_hdmi.txt. The DWC HDMI shall have between one and four ports,
28 or the functionally-reduced I2C master contained in the DWC HDMI. When
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| /freebsd/sys/contrib/device-tree/Bindings/display/rockchip/ |
| H A D | dw_hdmi-rockchip.txt | 1 Rockchip DWC HDMI TX Encoder
7 These DT bindings follow the Synopsys DWC HDMI TX bindings defined in
24 - ports: See dw_hdmi.txt. The DWC HDMI shall have a single port numbered 0
32 or the functionally-reduced I2C master contained in the DWC HDMI. When
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| H A D | rockchip,dw-hdmi.yaml | 7 title: Rockchip DWC HDMI TX Encoder
99 description: Input of the DWC HDMI TX
109 description: Output of the DWC HDMI TX
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| /freebsd/sys/dev/dwc/ |
| H A D | if_dwc_socfpga.c | 50 #include <dev/dwc/if_dwcvar.h>
51 #include <dev/dwc/dwc1000_reg.h>
102 DEFINE_CLASS_1(dwc, dwc_socfpga_driver, dwc_socfpga_methods,
107 MODULE_DEPEND(dwc_socfpga, dwc, 1, 1, 1);
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| H A D | if_dwc_aw.c | 50 #include <dev/dwc/if_dwcvar.h>
51 #include <dev/dwc/dwc1000_reg.h>
143 DEFINE_CLASS_1(dwc, a20_dwc_driver, a20_dwc_methods, sizeof(struct dwc_softc),
147 MODULE_DEPEND(a20_dwc, dwc, 1, 1, 1);
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| H A D | if_dwc.c | 71 #include <dev/dwc/if_dwcvar.h>
72 #include <dev/dwc/dwc1000_core.h>
73 #include <dev/dwc/dwc1000_dma.h>
689 "dwc",
694 DRIVER_MODULE(dwc, simplebus, dwc_driver, 0, 0);
695 DRIVER_MODULE(miibus, dwc, miibus_driver, 0, 0);
697 MODULE_DEPEND(dwc, ether, 1, 1, 1);
698 MODULE_DEPEND(dwc, miibus, 1, 1, 1);
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| H A D | if_dwc_if.m | 30 #include <dev/dwc/dwc1000_reg.h>
63 # Return the DWC MII clock for a specific hardware.
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| /freebsd/sys/contrib/device-tree/Bindings/pci/ |
| H A D | snps,dw-pcie-common.yaml | 7 title: Synopsys DWC PCIe RP/EP controller
22 DWC PCIe CSR space is normally accessed over the dedicated Data Bus
63 DWC PCIe reference manual explicitly defines a set of the clocks required
132 DWC PCIe reference manual explicitly defines a set of the reset
186 implied by the DWC PCIe controller they are attached to.
260 registers. This feature has been available since DWC PCIe v4.80a.
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| H A D | snps,dw-pcie.yaml | 16 # Please create a separate DT-schema for your DWC PCIe Root Port controller
53 Basic DWC PCIe controller configuration-space accessible over
57 via the PL viewports on the DWC PCIe controllers older than
61 Shadow DWC PCIe config-space registers. This space is selected
124 DWC PCIe Root Port/Complex specific IRQ signals. At least MSI interrupt
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| H A D | snps,dw-pcie-ep.yaml | 16 # Please create a separate DT-schema for your DWC PCIe Endpoint controller
44 Basic DWC PCIe controller configuration-space accessible over
48 via the PL viewports on the DWC PCIe controllers older than
52 Shadow DWC PCIe config-space registers. This space is selected
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| /freebsd/crypto/openssl/crypto/des/asm/ |
| H A D | desboth.pl | 54 &mov(&swtmp(2), (DWC(($enc)?"1":"0")));
58 &mov(&swtmp(2), (DWC(($enc)?"0":"1")));
62 &mov(&swtmp(2), (DWC(($enc)?"1":"0")));
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| /freebsd/sys/arm64/conf/ |
| H A D | std.rockchip | 41 device dwc # Synopsys DesignWare GMAC controller
51 device dwc3 # Synopsys DWC controller
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| /freebsd/tools/kerneldoc/subsys/ |
| H A D | Doxyfile-dev_dwc | 6 PROJECT_NAME = "FreeBSD kernel dwc device code"
12 INPUT = $(DOXYGEN_SRC_PATH)/dev/dwc/ \
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| /freebsd/sys/arm/allwinner/ |
| H A D | files.allwinner | 24 dev/dwc/if_dwc_aw.c optional dwc
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| /freebsd/sys/contrib/device-tree/Bindings/display/ |
| H A D | allwinner,sun8i-a83t-dw-hdmi.yaml | 7 title: Allwinner A83t DWC HDMI TX Encoder
14 These DT bindings follow the Synopsys DWC HDMI TX bindings defined
82 Phandle to the DWC HDMI PHY.
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