| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dsi.c | 239 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
241 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
243 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
246 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
249 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); in mtk_dsi_phy_timconfig()
250 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
287 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); in mtk_dsi_phy_timconfig()
288 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); in mtk_dsi_phy_timconfig()
289 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); in mtk_dsi_phy_timconfig()
290 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); in mtk_dsi_phy_timconfig()
[all …]
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| /linux/drivers/gpu/drm/bridge/synopsys/ |
| H A D | dw-mipi-dsi.c | 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
230 #define VPG_DEFS(name, dsi) \ argument
231 ((void __force *)&((*dsi).vpg_defs.name))
233 #define REGISTER(name, mask, dsi) \ argument
234 { #name, VPG_DEFS(name, dsi), mask, dsi }
240 struct dw_mipi_dsi *dsi; member
269 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
270 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
279 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) in dw_mipi_is_dual_mode() argument
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| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | dsi.c | 7 #define DSS_SUBSYS_NAME "DSI"
48 #include "dsi.h"
50 #define REG_GET(dsi, idx, start, end) \ argument
51 FLD_GET(dsi_read_reg(dsi, idx), start, end)
53 #define REG_FLD_MOD(dsi, idx, val, start, end) \ argument
54 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
56 static int dsi_init_dispc(struct dsi_data *dsi);
57 static void dsi_uninit_dispc(struct dsi_data *dsi);
59 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel);
61 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc,
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| /linux/drivers/gpu/drm/ |
| H A D | drm_mipi_dsi.c | 2 * MIPI DSI Bus
45 * DOC: dsi helpers
47 * These functions contain some common logic and helpers to deal with MIPI DSI
50 * Helpers are provided for a number of standard MIPI DSI command as well as a
56 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in mipi_dsi_device_match() local
62 /* compare DSI device and driver names */ in mipi_dsi_device_match()
63 if (!strcmp(dsi->name, drv->name)) in mipi_dsi_device_match()
71 const struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in mipi_dsi_uevent() local
79 dsi->name); in mipi_dsi_uevent()
96 .name = "mipi-dsi",
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | dsi.c | 30 #include "dsi.h"
103 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
105 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
108 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
110 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
112 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
117 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
120 trace_dsi_writel(dsi->dev, offset, value); in tegra_dsi_writel()
121 writel(value, dsi->regs + (offset << 2)); in tegra_dsi_writel()
203 struct tegra_dsi *dsi = node->info_ent->data; in tegra_dsi_show_regs() local
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| /linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_mipi_dsi.c | 3 * R-Car MIPI DSI Encoder
71 struct clk *dsi; member
178 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data) in rcar_mipi_dsi_write() argument
180 iowrite32(data, dsi->mmio + reg); in rcar_mipi_dsi_write()
183 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg) in rcar_mipi_dsi_read() argument
185 return ioread32(dsi->mmio + reg); in rcar_mipi_dsi_read()
188 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr) in rcar_mipi_dsi_clr() argument
190 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr); in rcar_mipi_dsi_clr()
193 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set) in rcar_mipi_dsi_set() argument
195 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set); in rcar_mipi_dsi_set()
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun6i_mipi_dsi.c | 291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
314 static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi, in sun6i_dsi_inst_setup() argument
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
329 static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi, in sun6i_dsi_inst_init() argument
334 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP, in sun6i_dsi_inst_init()
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| /linux/drivers/gpu/drm/renesas/rz-du/ |
| H A D | rzg2l_mipi_dsi.c | 3 * RZ/G2L MIPI DSI Encoder Driver
45 int (*dphy_init)(struct rzg2l_mipi_dsi *dsi, u64 hsfreq_millihz);
46 void (*dphy_startup_late_init)(struct rzg2l_mipi_dsi *dsi);
47 void (*dphy_exit)(struct rzg2l_mipi_dsi *dsi);
48 int (*dphy_conf_clks)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq,
50 unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi,
238 * enum rzv2h_dsi_timing_idx - MIPI DSI timing parameter indices
240 * These enums correspond to different MIPI DSI PHY timing parameters.
452 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) in rzg2l_mipi_dsi_phy_write() argument
454 iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg); in rzg2l_mipi_dsi_phy_write()
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| /linux/drivers/gpu/drm/bridge/ |
| H A D | samsung-dsim.c | 703 static inline void samsung_dsim_write(struct samsung_dsim *dsi, in samsung_dsim_write() argument
706 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_write()
709 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) in samsung_dsim_read() argument
711 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_read()
714 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi) in samsung_dsim_wait_for_reset() argument
716 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) in samsung_dsim_wait_for_reset()
719 dev_err(dsi->dev, "timeout waiting for reset\n"); in samsung_dsim_wait_for_reset()
722 static void samsung_dsim_reset(struct samsung_dsim *dsi) in samsung_dsim_reset() argument
724 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; in samsung_dsim_reset()
726 reinit_completion(&dsi->completed); in samsung_dsim_reset()
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| /linux/drivers/gpu/drm/bridge/cadence/ |
| H A D | cdns-dsi-core.c | 26 #include "cdns-dsi-core.h"
28 #include "cdns-dsi-j721e.h"
471 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
475 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
520 static int cdns_dsi_check_conf(struct cdns_dsi *dsi, in cdns_dsi_check_conf() argument
524 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_check_conf()
529 ret = cdns_dsi_mode2cfg(dsi, vm, dsi_cfg); in cdns_dsi_check_conf()
539 ret = phy_validate(dsi->dphy, PHY_MODE_MIPI_DPHY, 0, &output->phy_opts); in cdns_dsi_check_conf()
551 struct cdns_dsi *dsi = input_to_dsi(input); in cdns_dsi_bridge_attach() local
552 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_bridge_attach()
[all …]
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| /linux/drivers/gpu/drm/bridge/imx/ |
| H A D | imx93-mipi-dsi.c | 203 static void dphy_pll_write(struct imx93_dsi *dsi, unsigned int reg, u32 value) in dphy_pll_write() argument
207 ret = regmap_write(dsi->regmap, reg, value); in dphy_pll_write()
209 dev_err(dsi->dev, "failed to write 0x%08x to pll reg 0x%x: %d\n", in dphy_pll_write()
220 dphy_pll_get_configure_from_opts(struct imx93_dsi *dsi, in dphy_pll_get_configure_from_opts() argument
224 struct device *dev = dsi->dev; in dphy_pll_get_configure_from_opts()
225 unsigned long fin = dsi->ref_clk_rate; in dphy_pll_get_configure_from_opts()
296 static void dphy_pll_clear_shadow(struct imx93_dsi *dsi) in dphy_pll_clear_shadow() argument
300 dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN); in dphy_pll_clear_shadow()
304 dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN | SHADOW_CLR); in dphy_pll_clear_shadow()
308 dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN); in dphy_pll_clear_shadow()
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | mipi-dsi-bus.txt | 1 MIPI DSI (Display Serial Interface) busses
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
34 conjunction with another DSI host to drive the same peripheral. Hardware
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| H A D | allwinner,sun6i-a31-mipi-dsi.yaml | 4 $id: http://devicetree.org/schemas/display/allwinner,sun6i-a31-mipi-dsi.yaml#
7 title: Allwinner A31 MIPI-DSI Controller
17 - allwinner,sun6i-a31-mipi-dsi
18 - allwinner,sun50i-a64-mipi-dsi
19 - allwinner,sun50i-a100-mipi-dsi
21 - const: allwinner,sun20i-d1-mipi-dsi
22 - const: allwinner,sun50i-a100-mipi-dsi
44 vcc-dsi-supply:
45 description: VCC-DSI power supply of the DSI encoder
70 - $ref: dsi-controller.yaml#
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| /linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | dsi.c | 3 * linux/drivers/video/omap2/dss/dsi.c
9 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
213 /* DSI PLL HSDIV indices */
435 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_write_reg() local
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
451 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_read_reg() local
455 case DSI_PROTO: base = dsi->proto_base; break; in dsi_read_reg()
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| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-jdi-lt070me05000.c | 31 struct mipi_dsi_device *dsi; member
50 struct mipi_dsi_device *dsi = jdi->dsi; in jdi_panel_init() local
51 struct device *dev = &jdi->dsi->dev; in jdi_panel_init()
54 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in jdi_panel_init()
56 ret = mipi_dsi_dcs_soft_reset(dsi); in jdi_panel_init()
62 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT << 4); in jdi_panel_init()
68 ret = mipi_dsi_dcs_set_column_address(dsi, 0, jdi->mode->hdisplay - 1); in jdi_panel_init()
74 ret = mipi_dsi_dcs_set_page_address(dsi, 0, jdi->mode->vdisplay - 1); in jdi_panel_init()
86 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, in jdi_panel_init()
94 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_POWER_SAVE, in jdi_panel_init()
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| H A D | Kconfig | 56 uses 24 bit RGB per pixel. It provides a MIPI DSI interface to
57 the host and backlight is controlled through DSI commands.
67 24 bit RGB per pixel. It provides a MIPI DSI interface to
71 tristate "BOE TD4320 DSI panel"
87 resolution and uses 24 bit RGB per pixel. It provides a MIPI DSI
97 45NA WUXGA PANEL DSI Video Mode panel
106 WUXGA PANEL DSI Video Mode panel
116 The panel has a resolution of 1080x2246. It provides a MIPI DSI
126 KD35T133 controller for 320x480 LCD panels with MIPI-DSI
136 4-lane 800x1280 MIPI DSI panel.
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| H A D | panel-startek-kd070fhfid015.c | 43 struct mipi_dsi_device *dsi; member
54 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_init() local
55 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_init()
83 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_on() local
84 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_on()
95 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_off() local
96 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_off()
98 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in stk_panel_off()
195 struct mipi_dsi_device *dsi = bl_get_data(bl); in dsi_dcs_bl_get_brightness() local
199 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in dsi_dcs_bl_get_brightness()
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| H A D | panel-samsung-sofef00.c | 3 * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree:
23 struct mipi_dsi_device *dsi; member
57 struct mipi_dsi_device *dsi = ctx->dsi; in sofef00_panel_on() local
58 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in sofef00_panel_on()
60 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in sofef00_panel_on()
83 struct mipi_dsi_multi_context dsi_ctx = { .dsi = ctx->dsi }; in sofef00_enable()
92 struct mipi_dsi_device *dsi = ctx->dsi; in sofef00_panel_off() local
93 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in sofef00_panel_off()
177 struct mipi_dsi_device *dsi = bl_get_data(bl); in sofef00_panel_bl_update_status() local
181 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in sofef00_panel_bl_update_status()
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| H A D | panel-novatek-nt37801.c | 22 struct mipi_dsi_device *dsi; member
57 struct mipi_dsi_device *dsi = ctx->dsi; in novatek_nt37801_on() local
58 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in novatek_nt37801_on()
60 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in novatek_nt37801_on()
114 struct mipi_dsi_device *dsi = ctx->dsi; in novatek_nt37801_off() local
115 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in novatek_nt37801_off()
117 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in novatek_nt37801_off()
131 struct device *dev = &ctx->dsi->dev; in novatek_nt37801_prepare()
148 ret = mipi_dsi_picture_parameter_set(ctx->dsi, &pps); in novatek_nt37801_prepare()
154 ret = mipi_dsi_compression_mode(ctx->dsi, true); in novatek_nt37801_prepare()
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| H A D | panel-samsung-s6e63m0-dsi.c | 3 * DSI interface to the Samsung S6E63M0 panel.
22 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_read() local
25 ret = mipi_dsi_dcs_read(dsi, cmd, data, 1); in s6e63m0_dsi_dcs_read()
31 dev_dbg(dev, "DSI read CMD %02x = %02x\n", cmd, *data); in s6e63m0_dsi_dcs_read()
39 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_write() local
47 dev_dbg(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); in s6e63m0_dsi_dcs_write()
59 ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk); in s6e63m0_dsi_dcs_write()
71 ret = mipi_dsi_dcs_write(dsi, MCS_GLOBAL_PARAM, &cmdwritten, 1); in s6e63m0_dsi_dcs_write()
77 ret = mipi_dsi_dcs_write(dsi, cmd, seqp, chunk); in s6e63m0_dsi_dcs_write()
92 static int s6e63m0_dsi_probe(struct mipi_dsi_device *dsi) in s6e63m0_dsi_probe() argument
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| H A D | panel-ronbo-rb070d30.c | 29 struct mipi_dsi_device *dsi; member
52 dev_err(&ctx->dsi->dev, "Failed to enable supply: %d\n", ret); in rb070d30_panel_prepare()
79 return mipi_dsi_dcs_exit_sleep_mode(ctx->dsi); in rb070d30_panel_enable()
86 return mipi_dsi_dcs_enter_sleep_mode(ctx->dsi); in rb070d30_panel_disable()
114 dev_err(&ctx->dsi->dev, "Failed to add mode " DRM_MODE_FMT "\n", in rb070d30_panel_get_modes()
141 static int rb070d30_panel_dsi_probe(struct mipi_dsi_device *dsi) in rb070d30_panel_dsi_probe() argument
146 ctx = devm_drm_panel_alloc(&dsi->dev, struct rb070d30_panel, panel, in rb070d30_panel_dsi_probe()
152 ctx->supply = devm_regulator_get(&dsi->dev, "vcc-lcd"); in rb070d30_panel_dsi_probe()
156 mipi_dsi_set_drvdata(dsi, ctx); in rb070d30_panel_dsi_probe()
157 ctx->dsi = dsi; in rb070d30_panel_dsi_probe()
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| H A D | panel-sony-td4353-jdi.c | 5 * Generated with linux-mdss-dsi-panel-driver-generator with a
35 struct mipi_dsi_device *dsi; member
49 struct mipi_dsi_device *dsi = ctx->dsi; in sony_td4353_jdi_on() local
50 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in sony_td4353_jdi_on()
52 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in sony_td4353_jdi_on()
74 struct mipi_dsi_device *dsi = ctx->dsi; in sony_td4353_jdi_off() local
75 struct mipi_dsi_multi_context dsi_ctx = { .dsi = dsi }; in sony_td4353_jdi_off()
77 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in sony_td4353_jdi_off()
172 static int sony_td4353_jdi_probe(struct mipi_dsi_device *dsi) in sony_td4353_jdi_probe() argument
174 struct device *dev = &dsi->dev; in sony_td4353_jdi_probe()
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| H A D | panel-osd-osd101t2587-53ts.c | 20 struct mipi_dsi_device *dsi; member
37 ret = mipi_dsi_shutdown_peripheral(osd101t2587->dsi); in osd101t2587_panel_disable()
63 ret = mipi_dsi_turn_on_peripheral(osd101t2587->dsi); in osd101t2587_panel_enable()
128 struct device *dev = &osd101t2587->dsi->dev; in osd101t2587_panel_add()
144 static int osd101t2587_panel_probe(struct mipi_dsi_device *dsi) in osd101t2587_panel_probe() argument
150 id = of_match_node(osd101t2587_of_match, dsi->dev.of_node); in osd101t2587_panel_probe()
154 dsi->lanes = 4; in osd101t2587_panel_probe()
155 dsi->format = MIPI_DSI_FMT_RGB888; in osd101t2587_panel_probe()
156 dsi->mode_flags = MIPI_DSI_MODE_VIDEO | in osd101t2587_panel_probe()
161 osd101t2587 = devm_drm_panel_alloc(&dsi->dev, __typeof(*osd101t2587), base, in osd101t2587_panel_probe()
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| /linux/Documentation/devicetree/bindings/display/tegra/ |
| H A D | nvidia,tegra20-dsi.yaml | 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
20 - nvidia,tegra124-dsi
21 - nvidia,tegra210-dsi
22 - nvidia,tegra186-dsi
25 - const: nvidia,tegra132-dsi
26 - const: nvidia,tegra124-dsi
48 - const: dsi
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| /linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | dsi-phy-14nm.yaml | 4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
7 title: Qualcomm Display DSI 14nm PHY
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-14nm
19 - qcom,dsi-phy-14nm-2290
20 - qcom,dsi-phy-14nm-660
21 - qcom,dsi-phy-14nm-8953
22 - qcom,sm6125-dsi-phy-14nm
23 - qcom,sm6150-dsi-phy-14nm
27 - description: dsi phy register set
[all …]
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