| /linux/drivers/gpu/drm/bridge/ |
| H A D | nwl-dsi.c | 3 * i.MX8 NWL MIPI DSI host driver
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
83 * DSI data
85 * TODO: Since panel_bridges do their DSI setup in enable we
94 /* DSI clocks */
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| H A D | samsung-dsim.c | 533 static inline void samsung_dsim_write(struct samsung_dsim *dsi, in samsung_dsim_write() argument
536 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_write()
539 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) in samsung_dsim_read() argument
541 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_read()
544 static void samsung_dsim_wait_for_reset(struct samsung_dsim *dsi) in samsung_dsim_wait_for_reset() argument
546 if (wait_for_completion_timeout(&dsi->completed, msecs_to_jiffies(300))) in samsung_dsim_wait_for_reset()
549 dev_err(dsi->dev, "timeout waiting for reset\n"); in samsung_dsim_wait_for_reset()
552 static void samsung_dsim_reset(struct samsung_dsim *dsi) in samsung_dsim_reset() argument
554 u32 reset_val = dsi->driver_data->reg_values[RESET_TYPE]; in samsung_dsim_reset()
556 reinit_completion(&dsi->completed); in samsung_dsim_reset()
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| /linux/drivers/gpu/drm/mediatek/ |
| H A D | mtk_dsi.c | 238 static void mtk_dsi_mask(struct mtk_dsi *dsi, u32 offset, u32 mask, u32 data) in mtk_dsi_mask() argument
240 u32 temp = readl(dsi->regs + offset); in mtk_dsi_mask()
242 writel((temp & ~mask) | (data & mask), dsi->regs + offset); in mtk_dsi_mask()
245 static void mtk_dsi_phy_timconfig(struct mtk_dsi *dsi) in mtk_dsi_phy_timconfig() argument
248 u32 data_rate_mhz = DIV_ROUND_UP(dsi->data_rate, HZ_PER_MHZ); in mtk_dsi_phy_timconfig()
249 struct mtk_phy_timing *timing = &dsi->phy_timing; in mtk_dsi_phy_timconfig()
286 writel(timcon0, dsi->regs + DSI_PHY_TIMECON0); in mtk_dsi_phy_timconfig()
287 writel(timcon1, dsi->regs + DSI_PHY_TIMECON1); in mtk_dsi_phy_timconfig()
288 writel(timcon2, dsi->regs + DSI_PHY_TIMECON2); in mtk_dsi_phy_timconfig()
289 writel(timcon3, dsi->regs + DSI_PHY_TIMECON3); in mtk_dsi_phy_timconfig()
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| /linux/drivers/gpu/drm/bridge/synopsys/ |
| H A D | dw-mipi-dsi.c | 7 * This generic Synopsys DesignWare MIPI DSI host driver is based on the
8 * Rockchip version from rockchip/dw-mipi-dsi.c with phy & bridge APIs.
229 #define VPG_DEFS(name, dsi) \ argument
230 ((void __force *)&((*dsi).vpg_defs.name))
232 #define REGISTER(name, mask, dsi) \ argument
233 { #name, VPG_DEFS(name, dsi), mask, dsi }
239 struct dw_mipi_dsi *dsi; member
268 struct dw_mipi_dsi *master; /* dual-dsi master ptr */
269 struct dw_mipi_dsi *slave; /* dual-dsi slave ptr */
278 static inline bool dw_mipi_is_dual_mode(struct dw_mipi_dsi *dsi) in dw_mipi_is_dual_mode() argument
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| /linux/drivers/gpu/drm/omapdrm/dss/ |
| H A D | dsi.c | 7 #define DSS_SUBSYS_NAME "DSI"
48 #include "dsi.h"
50 #define REG_GET(dsi, idx, start, end) \ argument
51 FLD_GET(dsi_read_reg(dsi, idx), start, end)
53 #define REG_FLD_MOD(dsi, idx, val, start, end) \ argument
54 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
56 static int dsi_init_dispc(struct dsi_data *dsi);
57 static void dsi_uninit_dispc(struct dsi_data *dsi);
59 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel);
61 static ssize_t _omap_dsi_host_transfer(struct dsi_data *dsi, int vc,
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| /linux/drivers/gpu/drm/rockchip/ |
| H A D | dw-mipi-dsi-rockchip.c | 368 static inline void dsi_write(struct dw_mipi_dsi_rockchip *dsi, u32 reg, u32 val) in dsi_write() argument
370 writel(val, dsi->base + reg); in dsi_write()
373 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi_rockchip *dsi, in dw_mipi_dsi_phy_write() argument
382 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
384 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
387 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
389 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
392 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
398 static inline unsigned int ns2bc(struct dw_mipi_dsi_rockchip *dsi, int ns) in ns2bc() argument
400 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
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| /linux/drivers/gpu/drm/tegra/ |
| H A D | dsi.c | 29 #include "dsi.h"
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
119 trace_dsi_writel(dsi->dev, offset, value); in tegra_dsi_writel()
120 writel(value, dsi->regs + (offset << 2)); in tegra_dsi_writel()
202 struct tegra_dsi *dsi = node->info_ent->data; in tegra_dsi_show_regs() local
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| /linux/drivers/gpu/drm/renesas/rz-du/ |
| H A D | rzg2l_mipi_dsi.c | 3 * RZ/G2L MIPI DSI Encoder Driver
163 static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) in rzg2l_mipi_dsi_phy_write() argument
165 iowrite32(data, dsi->mmio + reg); in rzg2l_mipi_dsi_phy_write()
168 static void rzg2l_mipi_dsi_link_write(struct rzg2l_mipi_dsi *dsi, u32 reg, u32 data) in rzg2l_mipi_dsi_link_write() argument
170 iowrite32(data, dsi->mmio + LINK_REG_OFFSET + reg); in rzg2l_mipi_dsi_link_write()
173 static u32 rzg2l_mipi_dsi_phy_read(struct rzg2l_mipi_dsi *dsi, u32 reg) in rzg2l_mipi_dsi_phy_read() argument
175 return ioread32(dsi->mmio + reg); in rzg2l_mipi_dsi_phy_read()
178 static u32 rzg2l_mipi_dsi_link_read(struct rzg2l_mipi_dsi *dsi, u32 reg) in rzg2l_mipi_dsi_link_read() argument
180 return ioread32(dsi->mmio + LINK_REG_OFFSET + reg); in rzg2l_mipi_dsi_link_read()
187 static int rzg2l_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, in rzg2l_mipi_dsi_dphy_init() argument
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| /linux/drivers/gpu/drm/ |
| H A D | drm_mipi_dsi.c | 2 * MIPI DSI Bus
42 * DOC: dsi helpers
44 * These functions contain some common logic and helpers to deal with MIPI DSI
47 * Helpers are provided for a number of standard MIPI DSI command as well as a
53 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in mipi_dsi_device_match() local
59 /* compare DSI device and driver names */ in mipi_dsi_device_match()
60 if (!strcmp(dsi->name, drv->name)) in mipi_dsi_device_match()
68 const struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in mipi_dsi_uevent() local
76 dsi->name); in mipi_dsi_uevent()
93 .name = "mipi-dsi",
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| /linux/drivers/gpu/drm/renesas/rcar-du/ |
| H A D | rcar_mipi_dsi.c | 3 * R-Car MIPI DSI Encoder
70 struct clk *dsi; member
176 static void rcar_mipi_dsi_write(struct rcar_mipi_dsi *dsi, u32 reg, u32 data) in rcar_mipi_dsi_write() argument
178 iowrite32(data, dsi->mmio + reg); in rcar_mipi_dsi_write()
181 static u32 rcar_mipi_dsi_read(struct rcar_mipi_dsi *dsi, u32 reg) in rcar_mipi_dsi_read() argument
183 return ioread32(dsi->mmio + reg); in rcar_mipi_dsi_read()
186 static void rcar_mipi_dsi_clr(struct rcar_mipi_dsi *dsi, u32 reg, u32 clr) in rcar_mipi_dsi_clr() argument
188 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) & ~clr); in rcar_mipi_dsi_clr()
191 static void rcar_mipi_dsi_set(struct rcar_mipi_dsi *dsi, u32 reg, u32 set) in rcar_mipi_dsi_set() argument
193 rcar_mipi_dsi_write(dsi, reg, rcar_mipi_dsi_read(dsi, reg) | set); in rcar_mipi_dsi_set()
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| /linux/drivers/gpu/drm/sun4i/ |
| H A D | sun6i_mipi_dsi.c | 291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
314 static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi, in sun6i_dsi_inst_setup() argument
321 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), in sun6i_dsi_inst_setup()
329 static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi, in sun6i_dsi_inst_init() argument
334 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP, in sun6i_dsi_inst_init()
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| /linux/drivers/gpu/drm/stm/ |
| H A D | dw_mipi_dsi-stm.c | 28 /* DSI digital registers & bit definitions */
32 /* DSI wrapper registers & bit definitions */
35 #define WCFGR_DSIM BIT(0) /* DSI Mode */
39 #define WCR_DSIEN BIT(3) /* DSI ENable */
63 /* dsi color format coding according to the datasheet */
86 struct dw_mipi_dsi *dsi; member
94 static inline void dsi_write(struct dw_mipi_dsi_stm *dsi, u32 reg, u32 val) in dsi_write() argument
96 writel(val, dsi->base + reg); in dsi_write()
99 static inline u32 dsi_read(struct dw_mipi_dsi_stm *dsi, u32 reg) in dsi_read() argument
101 return readl(dsi->base + reg); in dsi_read()
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| /linux/Documentation/devicetree/bindings/display/msm/ |
| H A D | dsi-controller-main.yaml | 4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
7 title: Qualcomm Display DSI controller
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
19 - qcom,msm8916-dsi-ctrl
20 - qcom,msm8953-dsi-ctrl
21 - qcom,msm8974-dsi-ctrl
22 - qcom,msm8976-dsi-ctrl
23 - qcom,msm8996-dsi-ctrl
24 - qcom,msm8998-dsi-ctrl
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| /linux/drivers/gpu/drm/panel/ |
| H A D | panel-visionox-r66451.c | 22 struct mipi_dsi_device *dsi; member
44 struct mipi_dsi_device *dsi = ctx->dsi; in visionox_r66451_on() local
46 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in visionox_r66451_on()
48 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x00); in visionox_r66451_on()
49 mipi_dsi_dcs_write_seq(dsi, 0xc2, in visionox_r66451_on()
52 mipi_dsi_dcs_write_seq(dsi, 0xd7, in visionox_r66451_on()
56 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x80); in visionox_r66451_on()
57 mipi_dsi_dcs_write_seq(dsi, 0xde, in visionox_r66451_on()
60 mipi_dsi_dcs_write_seq(dsi, 0xb0, 0x04); in visionox_r66451_on()
61 mipi_dsi_dcs_write_seq(dsi, 0xe8, 0x00, 0x02); in visionox_r66451_on()
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| H A D | panel-samsung-s6d7aa0.c | 3 * Samsung S6D7AA0 MIPI-DSI TFT LCD controller drm_panel driver.
29 struct mipi_dsi_device *dsi; member
67 struct mipi_dsi_device *dsi = ctx->dsi; in s6d7aa0_lock() local
70 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0xa5, 0xa5); in s6d7aa0_lock()
71 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0xa5, 0xa5); in s6d7aa0_lock()
73 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0x5a, 0x5a); in s6d7aa0_lock()
75 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD1, 0x5a, 0x5a); in s6d7aa0_lock()
76 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD2, 0x5a, 0x5a); in s6d7aa0_lock()
78 mipi_dsi_dcs_write_seq(dsi, MCS_PASSWD3, 0xa5, 0xa5); in s6d7aa0_lock()
86 struct mipi_dsi_device *dsi = ctx->dsi; in s6d7aa0_on() local
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| H A D | panel-samsung-sofef00.c | 3 * Generated with linux-mdss-dsi-panel-driver-generator from vendor device tree:
22 struct mipi_dsi_device *dsi; member
46 struct mipi_dsi_device *dsi = ctx->dsi; in sofef00_panel_on() local
47 struct device *dev = &dsi->dev; in sofef00_panel_on()
50 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in sofef00_panel_on()
52 ret = mipi_dsi_dcs_exit_sleep_mode(dsi); in sofef00_panel_on()
59 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
61 ret = mipi_dsi_dcs_set_tear_on(dsi, MIPI_DSI_DCS_TEAR_MODE_VBLANK); in sofef00_panel_on()
67 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0xa5, 0xa5); in sofef00_panel_on()
68 mipi_dsi_dcs_write_seq(dsi, 0xf0, 0x5a, 0x5a); in sofef00_panel_on()
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| H A D | panel-jdi-lt070me05000.c | 31 struct mipi_dsi_device *dsi; member
50 struct mipi_dsi_device *dsi = jdi->dsi; in jdi_panel_init() local
51 struct device *dev = &jdi->dsi->dev; in jdi_panel_init()
54 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in jdi_panel_init()
56 ret = mipi_dsi_dcs_soft_reset(dsi); in jdi_panel_init()
62 ret = mipi_dsi_dcs_set_pixel_format(dsi, MIPI_DCS_PIXEL_FMT_24BIT << 4); in jdi_panel_init()
68 ret = mipi_dsi_dcs_set_column_address(dsi, 0, jdi->mode->hdisplay - 1); in jdi_panel_init()
74 ret = mipi_dsi_dcs_set_page_address(dsi, 0, jdi->mode->vdisplay - 1); in jdi_panel_init()
86 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_CONTROL_DISPLAY, in jdi_panel_init()
94 ret = mipi_dsi_dcs_write(dsi, MIPI_DCS_WRITE_POWER_SAVE, in jdi_panel_init()
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| H A D | panel-startek-kd070fhfid015.c | 43 struct mipi_dsi_device *dsi; member
54 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_init() local
55 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_init()
83 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_on() local
84 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_on()
95 struct mipi_dsi_device *dsi = stk->dsi; in stk_panel_off() local
96 struct mipi_dsi_multi_context dsi_ctx = {.dsi = dsi}; in stk_panel_off()
98 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in stk_panel_off()
195 struct mipi_dsi_device *dsi = bl_get_data(bl); in dsi_dcs_bl_get_brightness() local
199 dsi->mode_flags &= ~MIPI_DSI_MODE_LPM; in dsi_dcs_bl_get_brightness()
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| /linux/drivers/gpu/drm/vc4/ |
| H A D | vc4_dsi.c | 9 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
10 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
550 /* General DSI hardware state. */
571 /* DSI channel for the panel we're connected to. */
578 /* Input clock from CPRMAN to the digital PHY, for the DSI
583 /* Input clock to the analog PHY, used to generate the DSI bit
588 /* HS Clocks generated within the DSI analog PHY. */
614 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) in dsi_dma_workaround_write() argument
616 struct drm_device *drm = dsi->bridge.dev; in dsi_dma_workaround_write()
617 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
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| /linux/include/drm/ |
| H A D | drm_mipi_dsi.h | 3 * MIPI DSI Bus
25 * struct mipi_dsi_msg - read/write DSI buffer
50 * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format
68 * struct mipi_dsi_host_ops - DSI bus operations
69 * @attach: attach DSI device to DSI host
70 * @detach: detach DSI device from DSI host
71 * @transfer: transmit a DSI packet
73 * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg
81 * Note that typically DSI packet transmission is atomic, so the .transfer()
92 struct mipi_dsi_device *dsi);
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| /linux/drivers/gpu/drm/bridge/cadence/ |
| H A D | cdns-dsi-core.c | 25 #include "cdns-dsi-core.h"
27 #include "cdns-dsi-j721e.h"
467 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
472 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
513 static int cdns_dsi_adjust_phy_config(struct cdns_dsi *dsi, in cdns_dsi_adjust_phy_config() argument
519 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_adjust_phy_config()
536 * Make sure DSI htotal is aligned on a lane boundary when calculating in cdns_dsi_adjust_phy_config()
562 static int cdns_dsi_check_conf(struct cdns_dsi *dsi, in cdns_dsi_check_conf() argument
567 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_check_conf()
573 ret = cdns_dsi_mode2cfg(dsi, mode, dsi_cfg, mode_valid_check); in cdns_dsi_check_conf()
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| /linux/drivers/gpu/drm/bridge/imx/ |
| H A D | imx93-mipi-dsi.c | 203 static void dphy_pll_write(struct imx93_dsi *dsi, unsigned int reg, u32 value) in dphy_pll_write() argument
207 ret = regmap_write(dsi->regmap, reg, value); in dphy_pll_write()
209 dev_err(dsi->dev, "failed to write 0x%08x to pll reg 0x%x: %d\n", in dphy_pll_write()
220 dphy_pll_get_configure_from_opts(struct imx93_dsi *dsi, in dphy_pll_get_configure_from_opts() argument
224 struct device *dev = dsi->dev; in dphy_pll_get_configure_from_opts()
225 unsigned long fin = dsi->ref_clk_rate; in dphy_pll_get_configure_from_opts()
296 static void dphy_pll_clear_shadow(struct imx93_dsi *dsi) in dphy_pll_clear_shadow() argument
300 dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN); in dphy_pll_clear_shadow()
304 dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN | SHADOW_CLR); in dphy_pll_clear_shadow()
308 dphy_pll_write(dsi, DSI_REG, CLKSEL_GEN); in dphy_pll_clear_shadow()
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| /linux/Documentation/devicetree/bindings/display/ |
| H A D | mipi-dsi-bus.txt | 1 MIPI DSI (Display Serial Interface) busses
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
26 bus. DSI peripherals are addressed using a 2-bit virtual channel number, so
34 conjunction with another DSI host to drive the same peripheral. Hardware
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| /linux/drivers/video/fbdev/omap2/omapfb/dss/ |
| H A D | dsi.c | 3 * linux/drivers/video/omap2/dss/dsi.c
9 #define DSS_SUBSYS_NAME "DSI"
47 /* DSI Protocol Engine */
213 /* DSI PLL HSDIV indices */
435 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_write_reg() local
439 case DSI_PROTO: base = dsi->proto_base; break; in dsi_write_reg()
440 case DSI_PHY: base = dsi->phy_base; break; in dsi_write_reg()
441 case DSI_PLL: base = dsi->pll_base; break; in dsi_write_reg()
451 struct dsi_data *dsi = dsi_get_dsidrv_data(dsidev); in dsi_read_reg() local
455 case DSI_PROTO: base = dsi->proto_base; break; in dsi_read_reg()
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| /linux/Documentation/devicetree/bindings/display/tegra/ |
| H A D | nvidia,tegra20-dsi.yaml | 4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
20 - nvidia,tegra124-dsi
21 - nvidia,tegra210-dsi
22 - nvidia,tegra186-dsi
25 - const: nvidia,tegra132-dsi
26 - const: nvidia,tegra124-dsi
48 - const: dsi
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