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/linux/drivers/gpu/drm/bridge/
H A Dtc358775.c1 // SPDX-License-Identifier: GPL-2.0
3 * TC358775 DSI to LVDS bridge driver
16 #include <linux/media-bus-format.h>
36 /* DSI D-PHY Layer Registers */
38 #define CLW_DPHYCONTRX 0x0020 /* Clock Lane DPHY Rx Control */
39 #define D0W_DPHYCONTRX 0x0024 /* Data Lane 0 DPHY Rx Control */
40 #define D1W_DPHYCONTRX 0x0028 /* Data Lane 1 DPHY Rx Control */
41 #define D2W_DPHYCONTRX 0x002C /* Data Lane 2 DPHY Rx Control */
42 #define D3W_DPHYCONTRX 0x0030 /* Data Lane 3 DPHY Rx Control */
43 #define COM_DPHYCONTRX 0x0038 /* DPHY Rx Common Control */
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H A Dlontium-lt9211.c1 // SPDX-License-Identifier: GPL-2.0
6 * 2xDSI/2xLVDS/1xDPI -> 2xDSI/2xLVDS/1xDPI
8 * 1xDSI -> 1xLVDS
17 #include <linux/media-bus-format.h>
40 /* DSI lane count - 0 means 4 lanes ; 1, 2, 3 means 1, 2, 3 lanes. */
47 struct mipi_dsi_device *dsi; member
106 return drm_bridge_attach(bridge->encoder, ctx->panel_bridge, in lt9211_attach()
107 &ctx->bridge, flags); in lt9211_attach()
116 ret = regmap_bulk_read(ctx->regmap, REG_CHIPID0, chipid, 3); in lt9211_read_chipid()
118 dev_err(ctx->dev, "Failed to read Chip ID: %d\n", ret); in lt9211_read_chipid()
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H A Dnwl-dsi.c1 // SPDX-License-Identifier: GPL-2.0+
3 * i.MX8 NWL MIPI DSI host driver
15 #include <linux/media-bus-format.h>
34 #include "nwl-dsi.h"
36 #define DRV_NAME "nwl-dsi"
77 * The DSI host controller needs this reset sequence according to NWL:
78 * 1. Deassert pclk reset to get access to DSI regs
79 * 2. Configure DSI Host and DPHY and enable DPHY
81 * 4. Send DSI cmds to configure peripheral (handled by panel drv)
83 * DSI data
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H A Dtc358764.c1 // SPDX-License-Identifier: GPL-2.0
24 #define FLD_MASK(start, end) (((1 << ((start) - (end) + 1)) - 1) << (end))
38 /* DSI layer registers */
39 #define DSI_STARTDSI 0x0204 /* START control bit of DSI-TX */
121 #define SYS_RST_I2CS BIT(0) /* Reset I2C-Slave controller */
122 #define SYS_RST_I2CM BIT(1) /* Reset I2C-Master controller */
125 #define SYS_RST_DSIRX BIT(4) /* Reset DSI-RX and App controller */
132 /* Lane enable PPI and DSI register bits */
160 int ret = ctx->error; in tc358764_clear_error()
162 ctx->error = 0; in tc358764_clear_error()
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H A Dlontium-lt9611.c1 // SPDX-License-Identifier: GPL-2.0
4 * Copyright (c) 2019-2020. Linaro Limited.
10 #include <linux/media-bus-format.h>
17 #include <sound/hdmi-codec.h>
96 { 0x8106, 0x40 }, /* port A rx current */ in lt9611_mipi_input_analog()
99 { 0x8111, 0x40 }, /* port B rx current */ in lt9611_mipi_input_analog()
103 { 0x811c, 0x03 }, /* PortA clk lane no-LP mode */ in lt9611_mipi_input_analog()
104 { 0x8120, 0x03 }, /* PortB clk lane with-LP mode */ in lt9611_mipi_input_analog()
107 return regmap_multi_reg_write(lt9611->regmap, reg_cfg, ARRAY_SIZE(reg_cfg)); in lt9611_mipi_input_analog()
122 if (lt9611->dsi1_node) in lt9611_mipi_input_digital()
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H A Dsamsung-dsim.c1 // SPDX-License-Identifier: GPL-2.0-only
18 #include <linux/media-bus-format.h>
25 #include <drm/bridge/samsung-dsim.h>
112 #define DSIM_MAIN_VRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 16)
113 #define DSIM_MAIN_HRESOL(x, num_bits) (((x) & ((1 << (num_bits)) - 1)) << 0)
501 * downstream driver - drivers/gpu/drm/bridge/sec-dsim.c
533 static inline void samsung_dsim_write(struct samsung_dsim *dsi, in samsung_dsim_write() argument
536 writel(val, dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_write()
539 static inline u32 samsung_dsim_read(struct samsung_dsim *dsi, enum reg_idx idx) in samsung_dsim_read() argument
541 return readl(dsi->reg_base + dsi->driver_data->reg_ofs[idx]); in samsung_dsim_read()
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/linux/drivers/gpu/drm/tegra/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
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/linux/drivers/gpu/drm/i915/display/
H A Dvlv_dsi_pll.c40 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
41 461, 486, 243, 377, 188, 350, 175, 343, 427, 213, /* 71 - 80 */
42 106, 53, 282, 397, 454, 227, 113, 56, 284, 142, /* 81 - 90 */
43 71, 35, 273, 136, 324, 418, 465, 488, 500, 506 /* 91 - 100 */
46 /* Get DSI clock from pixel clock */
53 /* DSI data rate = pixel clock * bits per pixel / lane count in dsi_clk_from_pclk()
71 drm_err(&dev_priv->drm, "DSI CLK Out of Range\n"); in dsi_calc_mnp()
72 return -ECHRNG; in dsi_calc_mnp()
89 delta = abs(target_dsi_clk - (m_min * ref_clk) / (p_min * n)); in dsi_calc_mnp()
95 * +/- the required clock in dsi_calc_mnp()
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dchipone,icn6211.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Chipone ICN6211 MIPI-DSI to RGB Converter bridge
10 - Jagan Teki <jagan@amarulasolutions.com>
13 ICN6211 is MIPI-DSI to RGB Converter bridge from chipone.
15 It has a flexible configuration of MIPI DSI signal input and
21 - chipone,icn6211
25 description: virtual channel number of a DSI peripheral
27 clock-names:
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H A Dtoshiba,tc358775.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Toshiba TC358775 DSI to LVDS bridge
10 - Vinay Simha BN <simhavcs@gmail.com>
13 This binding supports DSI to LVDS bridges TC358765 and TC358775
15 MIPI DSI-RX Data 4-lane, CLK 1-lane with data rates up to 800 Mbps/lane.
17 Up to 1600x1200 24-bit/pixel resolution for single-link LVDS display panel
19 Up to WUXGA (1920x1200 24-bit pixels) resolution for dual-link LVDS display
25 - toshiba,tc358765
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/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun20i-d1.c1 // SPDX-License-Identifier: GPL-2.0
6 * Copyright (c) 2021-2022 Samuel Holland <samuel@sholland.org>
14 #include "pinctrl-sunxi.h"
36 SUNXI_FUNCTION(0x6, "uart0"), /* RX */
37 SUNXI_FUNCTION(0x7, "uart2"), /* RX */
38 SUNXI_FUNCTION(0x8, "ir"), /* RX */
59 SUNXI_FUNCTION(0x7, "uart4"), /* RX */
60 SUNXI_FUNCTION(0x8, "can0"), /* RX */
81 SUNXI_FUNCTION(0x7, "uart5"), /* RX */
82 SUNXI_FUNCTION(0x8, "can1"), /* RX */
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/linux/arch/riscv/boot/dts/allwinner/
H A Dsunxi-d1s-t113.dtsi1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 // Copyright (C) 2021-2022 Samuel Holland <samuel@sholland.org>
4 #include <dt-bindings/clock/sun6i-rtc.h>
5 #include <dt-bindings/clock/sun8i-de2.h>
6 #include <dt-bindings/clock/sun8i-tcon-top.h>
7 #include <dt-bindings/clock/sun20i-d1-ccu.h>
8 #include <dt-bindings/clock/sun20i-d1-r-ccu.h>
9 #include <dt-bindings/interrupt-controller/irq.h>
10 #include <dt-bindings/reset/sun8i-de2.h>
11 #include <dt-bindings/reset/sun20i-d1-ccu.h>
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/linux/arch/arm/boot/dts/nvidia/
H A Dtegra114.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra114-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra114-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
11 interrupt-parent = <&lic>;
12 #address-cells = <1>;
13 #size-cells = <1>;
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H A Dtegra30.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra30-car.h>
3 #include <dt-bindings/gpio/tegra-gpio.h>
4 #include <dt-bindings/memory/tegra30-mc.h>
5 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
6 #include <dt-bindings/interrupt-controller/arm-gic.h>
7 #include <dt-bindings/soc/tegra-pmc.h>
8 #include <dt-bindings/thermal/thermal.h>
10 #include "tegra30-peripherals-opp.dtsi"
14 interrupt-parent = <&lic>;
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/linux/drivers/gpu/drm/sprd/
H A Dsprd_dsi.c1 // SPDX-License-Identifier: GPL-2.0
139 return (readl(ctx->base + offset) & mask) >> shift; in dsi_reg_rd()
148 ret = readl(ctx->base + offset); in dsi_reg_wr()
151 writel(ret, ctx->base + offset); in dsi_reg_wr()
158 u32 ret = readl(ctx->base + offset); in dsi_reg_up()
160 writel((ret & ~mask) | (val & mask), ctx->base + offset); in dsi_reg_up()
165 struct sprd_dsi *dsi = context; in regmap_tst_io_write() local
166 struct dsi_context *ctx = &dsi->ctx; in regmap_tst_io_write()
169 return -EINVAL; in regmap_tst_io_write()
171 drm_dbg(dsi->drm, "reg = 0x%02x, val = 0x%02x\n", reg, val); in regmap_tst_io_write()
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/linux/drivers/gpu/drm/bridge/cadence/
H A Dcdns-dsi-core.c1 // SPDX-License-Identifier: GPL-2.0
23 #include <linux/phy/phy-mipi-dphy.h>
25 #include "cdns-dsi-core.h"
27 #include "cdns-dsi-j721e.h"
72 #define DATA_LANE_EN(x) BIT((x) - 1)
448 return mode->hsync_start - mode->hdisplay; in mode_to_dpi_hfp()
450 return mode->crtc_hsync_start - mode->crtc_hdisplay; in mode_to_dpi_hfp()
462 dsi_timing -= dsi_pkt_overhead; in dpi_to_dsi_timing()
467 static int cdns_dsi_mode2cfg(struct cdns_dsi *dsi, in cdns_dsi_mode2cfg() argument
472 struct cdns_dsi_output *output = &dsi->output; in cdns_dsi_mode2cfg()
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/linux/arch/arm/boot/dts/st/
H A Dste-dbx5x0.dtsi1 // SPDX-License-Identifier: GPL-2.0-or-later
6 #include <dt-bindings/interrupt-controller/irq.h>
7 #include <dt-bindings/interrupt-controller/arm-gic.h>
8 #include <dt-bindings/clock/ste-db8500-clkout.h>
9 #include <dt-bindings/reset/stericsson,db8500-prcc-reset.h>
10 #include <dt-bindings/mfd/dbx500-prcmu.h>
11 #include <dt-bindings/arm/ux500_pm_domains.h>
12 #include <dt-bindings/gpio/gpio.h>
13 #include <dt-bindings/thermal/thermal.h>
16 #address-cells = <1>;
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/linux/drivers/gpu/drm/msm/dsi/
H A Ddsi_host.c1 // SPDX-License-Identifier: GPL-2.0-only
8 #include <linux/dma-mapping.h>
26 #include "dsi.h"
27 #include "dsi.xml.h"
44 return -EINVAL; in dsi_get_version()
48 * makes all other registers 4-byte shifted down. in dsi_get_version()
52 * 0x1f0). In the case of DSIv2, this hast to be a non-zero value. In in dsi_get_version()
59 /* older dsi host, there is no register shift */ in dsi_get_version()
67 return -EINVAL; in dsi_get_version()
83 return -EINVAL; in dsi_get_version()
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/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi1 // SPDX-License-Identifier: GPL-2.0
2 #include <dt-bindings/clock/tegra186-clock.h>
3 #include <dt-bindings/gpio/tegra186-gpio.h>
4 #include <dt-bindings/interrupt-controller/arm-gic.h>
5 #include <dt-bindings/mailbox/tegra186-hsp.h>
6 #include <dt-bindings/memory/tegra186-mc.h>
7 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
8 #include <dt-bindings/power/tegra186-powergate.h>
9 #include <dt-bindings/reset/tegra186-reset.h>
10 #include <dt-bindings/thermal/tegra186-bpmp-thermal.h>
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/linux/drivers/video/fbdev/mmp/hw/
H A Dmmp_ctrl.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
16 /* ------------< LCD register >------------ */
150 #define LCD_SCLK(path) ((PATH_PN == path->id) ? LCD_CFG_SCLK_DIV :\
151 ((PATH_TV == path->id) ? LCD_TCLK_DIV : LCD_PN2_SCLK_DIV))
386 #define CFG_RXBITS(rx) (((rx) - 1)<<16) /* 0x1F~0x1 */ argument
388 #define CFG_TXBITS(tx) (((tx) - 1)<<8) /* 0x1F~0x1 */
394 #define CFG_RXBITSTO0(rx) ((rx)<<5) argument
411 1. Smart Pannel 8-bit Bus Control Register.
685 /* FIXME - JUST GUESS */
811 /* read-only */
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/linux/Documentation/devicetree/bindings/phy/
H A Dallwinner,sun6i-a31-mipi-dphy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/phy/allwinner,sun6i-a31-mipi-dphy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner A31 MIPI D-PHY Controller
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 "#phy-cells":
19 - const: allwinner,sun6i-a31-mipi-dphy
20 - const: allwinner,sun50i-a100-mipi-dphy
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/linux/drivers/gpu/drm/bridge/analogix/
H A Danx7625.c1 // SPDX-License-Identifier: GPL-2.0-only
35 #include <media/v4l2-fwnode.h>
36 #include <sound/hdmi-codec.h>
50 struct device *dev = &client->dev; in i2c_access_workaround()
53 if (client == ctx->last_client) in i2c_access_workaround()
56 ctx->last_client = client; in i2c_access_workaround()
58 if (client == ctx->i2c.tcpc_client) in i2c_access_workaround()
60 else if (client == ctx->i2c.tx_p0_client) in i2c_access_workaround()
62 else if (client == ctx->i2c.tx_p1_client) in i2c_access_workaround()
64 else if (client == ctx->i2c.rx_p0_client) in i2c_access_workaround()
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/linux/arch/arm64/boot/dts/qcom/
H A Dsdm670.dtsi1 // SPDX-License-Identifier: GPL-2.0
9 #include <dt-bindings/clock/qcom,dispcc-sdm845.h>
10 #include <dt-bindings/clock/qcom,gcc-sdm845.h>
11 #include <dt-bindings/clock/qcom,rpmh.h>
12 #include <dt-bindings/dma/qcom-gpi.h>
13 #include <dt-bindings/gpio/gpio.h>
14 #include <dt-bindings/interconnect/qcom,osm-l3.h>
15 #include <dt-bindings/interconnect/qcom,sdm670-rpmh.h>
16 #include <dt-bindings/interrupt-controller/arm-gic.h>
17 #include <dt-bindings/phy/phy-qcom-qusb2.h>
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/linux/drivers/gpu/drm/omapdrm/dss/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
7 #define DSS_SUBSYS_NAME "DSI"
48 #include "dsi.h"
50 #define REG_GET(dsi, idx, start, end) \ argument
51 FLD_GET(dsi_read_reg(dsi, idx), start, end)
53 #define REG_FLD_MOD(dsi, idx, val, start, end) \ argument
54 dsi_write_reg(dsi, idx, FLD_MOD(dsi_read_reg(dsi, idx), val, start, end))
56 static int dsi_init_dispc(struct dsi_data *dsi);
57 static void dsi_uninit_dispc(struct dsi_data *dsi);
59 static int dsi_vc_send_null(struct dsi_data *dsi, int vc, int channel);
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/linux/drivers/gpu/drm/mcde/
H A Dmcde_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
32 /* PRCMU DSI reset registers */
73 d = host_to_mcde_dsi(mdsi->host); in mcde_dsi_irq()
75 dev_dbg(d->dev, "%s called\n", __func__); in mcde_dsi_irq()
77 val = readl(d->regs + DSI_DIRECT_CMD_STS_FLAG); in mcde_dsi_irq()
79 dev_dbg(d->dev, "DSI_DIRECT_CMD_STS_FLAG = %08x\n", val); in mcde_dsi_irq()
81 dev_dbg(d->dev, "direct command write completed\n"); in mcde_dsi_irq()
84 dev_dbg(d->dev, "direct command TE received\n"); in mcde_dsi_irq()
87 dev_err(d->dev, "direct command ACK ERR received\n"); in mcde_dsi_irq()
89 dev_err(d->dev, "direct command read ERR received\n"); in mcde_dsi_irq()
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