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/linux/Documentation/devicetree/bindings/display/
H A Dmipi-dsi-bus.txt1 MIPI DSI (Display Serial Interface) busses
4 The MIPI Display Serial Interface specifies a serial bus and a protocol for
5 communication between a host and up to four peripherals. This document will
6 define the syntax used to represent a DSI bus in a device tree.
8 This document describes DSI bus-specific properties only or defines existing
9 standard properties in the context of the DSI bus.
11 Each DSI host provides a DSI bus. The DSI host controller's node contains a
15 The following assumes that only a single peripheral is connected to a DSI
18 DSI host
22 a DSI host, the following properties apply to a node representing a DSI host.
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H A Dste,mcde.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: ST-Ericsson Multi Channel Display Engine MCDE
10 - Linus Walleij <linus.walleij@linaro.org>
25 - description: MCDECLK (main MCDE clock)
26 - description: LCDCLK (LCD clock)
27 - description: PLLDSI (HDMI clock)
29 clock-names:
31 - const: mcde
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H A Dst,stm32-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/st,stm32-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 DSI host controller
10 - Philippe Cornu <philippe.cornu@foss.st.com>
11 - Yannick Fertre <yannick.fertre@foss.st.com>
14 The STMicroelectronics STM32 DSI controller uses the Synopsys DesignWare MIPI-DSI host controller.
17 - $ref: dsi-controller.yaml#
21 const: st,stm32-dsi
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/linux/drivers/gpu/drm/panel/
H A DKconfig1 # SPDX-License-Identifier: GPL-2.0-only
17 Y030XX067A 320x480 3.0" panel as found in the YLM RG-280M, RG-300
18 and RG-99 handheld gaming consoles.
46 as found in the YLM RS-97 handheld gaming console.
49 tristate "Boe BF060Y8M-AJ0 panel"
54 Say Y here if you want to enable support for Boe BF060Y8M-AJ0
55 5.99" AMOLED modules. The panel has a 1080x2160 resolution and
56 uses 24 bit RGB per pixel. It provides a MIPI DSI interface to
57 the host and backlight is controlled through DSI commands.
66 TFT-LCD modules. The panel has a 1200x1920 resolution and uses
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H A Dpanel-raspberrypi-touchscreen.c2 * Copyright © 2016-2017 Broadcom
8 * Portions of this file (derived from panel-simple.c) are:
12 * Permission is hereby granted, free of charge, to any person obtaining a
25 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
35 * The 7" touchscreen consists of a DPI LCD panel, a Toshiba
36 * TC358762XBG DSI-DPI bridge, and an I2C-connected Atmel ATTINY88-MUR
40 * This driver controls the TC358762 and ATTINY88, presenting a DSI
41 * device with a drm_panel.
47 #include <linux/media-bus-format.h>
58 #define RPI_DSI_DRIVER_NAME "rpi-ts-dsi"
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H A Dpanel-ronbo-rb070d30.c1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2018-2019, Bridge Systems BV
4 * Copyright (C) 2018-2019, Bootlin
7 * This file based on panel-ilitek-ili9881c.c
15 #include <linux/media-bus-format.h>
29 struct mipi_dsi_device *dsi; member
50 ret = regulator_enable(ctx->supply); in rb070d30_panel_prepare()
52 dev_err(&ctx->dsi->dev, "Failed to enable supply: %d\n", ret); in rb070d30_panel_prepare()
57 gpiod_set_value_cansleep(ctx->gpios.power, 1); in rb070d30_panel_prepare()
59 gpiod_set_value_cansleep(ctx->gpios.reset, 1); in rb070d30_panel_prepare()
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H A Dpanel-sharp-lq101r1sx01.c1 // SPDX-License-Identifier: GPL-2.0-only
21 /* the datasheet refers to them as DSI-LINK1 and DSI-LINK2 */
37 unsigned int refresh = drm_mode_vrefresh(sharp->mode); in sharp_wait_frames()
48 struct mipi_dsi_device *dsi = sharp->link1; in sharp_panel_write() local
51 err = mipi_dsi_generic_write(dsi, payload, sizeof(payload)); in sharp_panel_write()
53 dev_err(&dsi->dev, "failed to write %02x to %04x: %zd\n", in sharp_panel_write()
58 err = mipi_dsi_dcs_nop(dsi); in sharp_panel_write()
60 dev_err(&dsi->dev, "failed to send DCS nop: %zd\n", err); in sharp_panel_write()
76 err = mipi_dsi_generic_read(sharp->link1, &offset, sizeof(offset), in sharp_panel_read()
79 dev_err(&sharp->link1->dev, "failed to read from %04x: %zd\n", in sharp_panel_read()
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H A Dpanel-panasonic-vvx10f034n00.c1 // SPDX-License-Identifier: GPL-2.0-only
23 * When power is turned off to this panel a minimum off time of 500ms has to be
31 struct mipi_dsi_device *dsi; member
47 return mipi_dsi_turn_on_peripheral(wuxga_nt->dsi); in wuxga_nt_panel_on()
54 return mipi_dsi_shutdown_peripheral(wuxga_nt->dsi); in wuxga_nt_panel_disable()
61 regulator_disable(wuxga_nt->supply); in wuxga_nt_panel_unprepare()
62 wuxga_nt->earliest_wake = ktime_add_ms(ktime_get_real(), MIN_POFF_MS); in wuxga_nt_panel_unprepare()
74 * If the user re-enabled the panel before the required off-time then in wuxga_nt_panel_prepare()
75 * we need to wait the remaining period before re-enabling regulator in wuxga_nt_panel_prepare()
77 enablewait = ktime_ms_delta(wuxga_nt->earliest_wake, ktime_get_real()); in wuxga_nt_panel_prepare()
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H A Dpanel-samsung-s6e63m0-dsi.c1 // SPDX-License-Identifier: GPL-2.0
3 * DSI interface to the Samsung S6E63M0 panel.
14 #include "panel-samsung-s6e63m0.h"
22 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_read() local
25 ret = mipi_dsi_dcs_read(dsi, cmd, data, 1); in s6e63m0_dsi_dcs_read()
31 dev_dbg(dev, "DSI read CMD %02x = %02x\n", cmd, *data); in s6e63m0_dsi_dcs_read()
39 struct mipi_dsi_device *dsi = to_mipi_dsi_device(dev); in s6e63m0_dsi_dcs_write() local
47 dev_dbg(dev, "DSI writing dcs seq: %*ph\n", (int)len, data); in s6e63m0_dsi_dcs_write()
53 remain = len - 1; in s6e63m0_dsi_dcs_write()
56 /* Send max S6E63M0_DSI_MAX_CHUNK bytes at a time */ in s6e63m0_dsi_dcs_write()
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/linux/Documentation/devicetree/bindings/display/tegra/
H A Dnvidia,tegra20-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/tegra/nvidia,tegra20-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <thierry.reding@gmail.com>
11 - Jon Hunter <jonathanh@nvidia.com>
16 - enum:
17 - nvidia,tegra20-dsi
18 - nvidia,tegra30-dsi
19 - nvidia,tegra114-dsi
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/linux/drivers/gpu/drm/sun4i/
H A Dsun6i_mipi_dsi.c1 // SPDX-License-Identifier: GPL-2.0+
4 * Copyright (C) 2017-2018 Bootlin
11 #include <linux/crc-ccitt.h>
14 #include <linux/phy/phy-mipi-dphy.h>
291 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) in sun6i_dsi_inst_abort() argument
293 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_abort()
297 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) in sun6i_dsi_inst_commit() argument
299 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_commit()
304 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) in sun6i_dsi_inst_wait_for_completion() argument
308 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, in sun6i_dsi_inst_wait_for_completion()
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/linux/Documentation/devicetree/bindings/display/msm/
H A Ddsi-phy-14nm.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-phy-14nm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI 14nm PHY
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
13 - $ref: dsi-phy-common.yaml#
18 - qcom,dsi-phy-14nm
19 - qcom,dsi-phy-14nm-2290
20 - qcom,dsi-phy-14nm-660
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H A Dqcom,sdm845-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Krishna Manikandan <quic_mkrishn@quicinc.com>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sdm845-mdss
25 - description: Display AHB clock from gcc
26 - description: Display core clock
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H A Dqcom,sdm670-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sdm670-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Richard Acayan <mailingradian@gmail.com>
13 SDM670 MSM Mobile Display Subsystem (MDSS), which encapsulates sub-blocks
14 like DPU display controller, DSI and DP interfaces etc.
16 $ref: /schemas/display/msm/mdss-common.yaml#
20 const: qcom,sdm670-mdss
24 - description: Display AHB clock from gcc
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H A Dqcom,msm8998-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,msm8998-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,msm8998-mdss
25 - description: Display AHB clock
26 - description: Display AXI clock
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H A Dqcom,sm8150-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8150-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
22 - const: qcom,sm8150-mdss
26 - description: Display AHB clock from gcc
27 - description: Display hf axi clock
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H A Dqcom,sm8250-mdss.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/qcom,sm8250-mdss.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
14 sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
17 $ref: /schemas/display/msm/mdss-common.yaml#
21 const: qcom,sm8250-mdss
25 - description: Display AHB clock from gcc
26 - description: Display hf axi clock
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/linux/Documentation/devicetree/bindings/display/panel/
H A Dpanel-dsi-cm.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/panel/panel-dsi-cm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: DSI command mode panels
10 - Tomi Valkeinen <tomi.valkeinen@ti.com>
11 - Sebastian Reichel <sre@kernel.org>
14 This binding file is a collection of the DSI panels that
16 referenced via the optional backlight property, the DSI
19 to the display, or it may be a direct child node of the
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H A Dsharp,lq101r1sx01.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Thierry Reding <treding@nvidia.com>
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
14 - left-right: each channel drives the left or right half of the screen
15 - even-odd: each channel drives the even or odd lines of the screen
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1), left or even, is considered the primary
19 peripheral and controls the device. The 'link2' property contains a phandle
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H A Djdi,lpm102a188a.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: JDI LPM102A188A 2560x1800 10.2" DSI Panel
10 - Diogo Ivo <diogo.ivo@tecnico.ulisboa.pt>
13 This panel requires a dual-channel DSI host to operate. It supports two modes:
14 - left-right: each channel drives the left or right half of the screen
15 - even-odd: each channel drives the even or odd lines of the screen
17 Each of the DSI channels controls a separate DSI peripheral. The peripheral
18 driven by the first link (DSI-LINK1) is considered the primary peripheral
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/linux/drivers/gpu/drm/tegra/
H A Ddsi.c1 // SPDX-License-Identifier: GPL-2.0-only
30 #include "dsi.h"
31 #include "mipi-phy.h"
82 /* for ganged-mode support */
103 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
105 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
108 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
110 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
112 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
117 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
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/linux/Documentation/devicetree/bindings/display/hisilicon/
H A Ddw-dsi.txt1 Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
3 A DSI Host Controller resides in the middle of display controller and external
7 - compatible: value should be "hisilicon,hi6220-dsi".
8 - reg: physical base address and length of dsi controller's registers.
9 - clocks: contains APB clock phandle + clock-specifier pair.
10 - clock-names: should be "pclk".
11 - ports: contains DSI controller input and output sub port.
17 A example of HiKey board hi6220 SoC and board specific DT entry:
21 dsi: dsi@f4107800 {
22 compatible = "hisilicon,hi6220-dsi";
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/linux/Documentation/devicetree/bindings/display/bridge/
H A Dnwl-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/nwl-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Northwest Logic MIPI-DSI controller on i.MX SoCs
10 - Guido Gúnther <agx@sigxcpu.org>
11 - Robert Chiras <robert.chiras@nxp.com>
14 NWL MIPI-DSI host controller found on i.MX8 platforms. This is a dsi bridge for
15 the SOCs NWL MIPI-DSI host controller.
18 - $ref: ../dsi-controller.yaml#
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H A Dfsl,imx93-mipi-dsi.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/display/bridge/fsl,imx93-mipi-dsi.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Freescale i.MX93 specific extensions to Synopsys Designware MIPI DSI
10 - Liu Ying <victor.liu@nxp.com>
13 There is a Synopsys Designware MIPI DSI Host Controller and a Synopsys
15 and extensions to them are controlled by i.MX93 media blk-ctrl.
18 - $ref: snps,dw-mipi-dsi.yaml#
22 const: fsl,imx93-mipi-dsi
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/linux/drivers/gpu/drm/msm/
H A DNOTES5 + MDP3 - ?? seems to be what is on geeksphone peak device
6 + MDP4 - S3 (APQ8060, touchpad), S4-pro (APQ8064, nexus4 & ifc6410)
7 + MDP5 - snapdragon 800
9 (I don't have a completely clear picture on which display controller
12 Plus a handful of blocks around them for HDMI/DSI/etc output.
18 But, HDMI/DSI/etc blocks seem like they can be shared across multiple
20 with N different kms devices from xf86-video-freedreno. Plus, it
27 And one or more 'struct msm_gpu' for the various different gpu sub-
38 plane -> PIPE{RGBn,VGn} \
39 crtc -> OVLP{n} + DMA{P,S,E} (??) |-> MDP "device"
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