| /linux/Documentation/devicetree/bindings/memory-controllers/ |
| H A D | rockchip,rk3399-dmc.yaml | 163 (including DQS/DQ/DM line) drive strength.
211 (including DQS/DQ/DM line) drive strength.
242 DQS/DQ line strength in ohms.
274 (including DQS/DQ/DM line) drive strength.
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| /linux/Documentation/devicetree/bindings/memory-controllers/ddr/ |
| H A D | jedec,lpddr2-timings.yaml | 35 DQS output data access time from CK_t/CK_c in pico seconds.
40 DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
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| H A D | jedec,lpddr3.yaml | 59 DQS output data access time from CK_t/CK_c in terms of number of clock
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| /linux/fs/xfs/ |
| H A D | xfs_trans_dquot.c | 90 oqa = otp->t_dqinfo->dqs[j]; in xfs_trans_dup_dqinfo()
91 nqa = ntp->t_dqinfo->dqs[j]; in xfs_trans_dup_dqinfo()
272 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_USR]; in xfs_trans_get_dqtrx()
275 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_GRP]; in xfs_trans_get_dqtrx()
278 qa = tp->t_dqinfo->dqs[XFS_QM_TRANS_PRJ]; in xfs_trans_get_dqtrx()
490 qa = tp->t_dqinfo->dqs[j]; in xfs_trans_apply_dquot_deltas()
675 qa = tp->t_dqinfo->dqs[j]; in xfs_trans_unreserve_and_mod_dquots()
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| H A D | xfs_qm.h | 62 xfs_filblks_t qi_dqchunklen; /* # BBs in a chunk of dqs */
142 struct xfs_dqtrx dqs[XFS_QM_TRANS_DQTYPES][XFS_QM_TRANS_MAXDQS]; member
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| /linux/Documentation/devicetree/bindings/mmc/ |
| H A D | nvidia,tegra20-sdhci.yaml | 100 The DQS trim values are only used on controllers which support HS400
108 nvidia,dqs-trim:
109 description: Specify DQS trim value for HS400 timing.
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| /linux/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/ |
| H A D | ali_drw.json | 297 "BriefDescription": "A DQS Oscillator MPC command to DRAM.",
304 "BriefDescription": "A DQS Oscillator MRR command to DRAM.",
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| /linux/drivers/memory/tegra/ |
| H A D | tegra210-emc-cc-r21021.c | 100 int dqs = (dev); \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
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| H A D | tegra124-emc.c | 640 /* Prepare DQ/DQS for clock change */ in tegra_emc_prepare_timing_change()
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| H A D | tegra30-emc.c | 600 /* check DQ/DQS VREF delay */ in emc_prepare_timing_change()
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| /linux/arch/arm64/boot/dts/freescale/ |
| H A D | imx93-tqma9352.dtsi | 61 * no DQS, RXCLKSRC internal loop back, max 66 MHz
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| /linux/drivers/pinctrl/sunxi/ |
| H A D | pinctrl-sun9i-a80.c | 242 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
253 SUNXI_FUNCTION(0x3, "nand0_b")), /* DQS */
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| H A D | pinctrl-sun8i-a33.c | 152 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| H A D | pinctrl-sun8i-h3.c | 230 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| H A D | pinctrl-sun8i-a23.c | 192 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| H A D | pinctrl-sun50i-h5.c | 235 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| H A D | pinctrl-sun8i-a83t.c | 170 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| H A D | pinctrl-sun50i-h6.c | 182 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| H A D | pinctrl-sun50i-h616.c | 170 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
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| /linux/drivers/spi/ |
| H A D | spi-cadence-xspi.c | 37 /* PHY DQS timing register */
501 "Incorrect DQS pulses detected\n"); in cdns_xspi_check_command_status()
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| /linux/arch/m68k/coldfire/ |
| H A D | m53xx.c | 538 /* wait for DQS logic to relock */ in clock_pll()
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| /linux/arch/arm/boot/dts/nvidia/ |
| H A D | tegra30-colibri.dtsi | 632 gmi-dqs-pi2 {
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| H A D | tegra114-asus-tf701t.dts | 971 gmi-dqs-p {
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| /linux/arch/arm/boot/dts/rockchip/ |
| H A D | rk3128.dtsi | 1149 flash_dqs: flash-dqs {
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| /linux/drivers/net/ethernet/mellanox/mlxsw/ |
| H A D | cmd.h | 1058 * SW should not post descriptors on nonoperational DQs.
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