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/linux/Documentation/devicetree/bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml163 (including DQS/DQ/DM line) drive strength.
211 (including DQS/DQ/DM line) drive strength.
242 DQS/DQ line strength in ohms.
274 (including DQS/DQ/DM line) drive strength.
/linux/Documentation/devicetree/bindings/memory-controllers/ddr/
H A Djedec,lpddr2-timings.yaml35 DQS output data access time from CK_t/CK_c in pico seconds.
40 DQS output data access time from CK_t/CK_c, temperature de-rated, in pico
/linux/Documentation/devicetree/bindings/mmc/
H A Dnvidia,tegra20-sdhci.yaml100 The DQS trim values are only used on controllers which support HS400
108 nvidia,dqs-trim:
109 description: Specify DQS trim value for HS400 timing.
/linux/tools/perf/pmu-events/arch/arm64/thead/yitian710/sys/
H A Dali_drw.json297 "BriefDescription": "A DQS Oscillator MPC command to DRAM.",
304 "BriefDescription": "A DQS Oscillator MRR command to DRAM.",
/linux/include/linux/mtd/
H A Drawnand.h507 * @tDQSCK_min: Start of the access window of DQS from CLK
508 * @tDQSCK_max: End of the access window of DQS from CLK
509 * @tDQSD_min: Min W/R_n low to DQS/DQ driven by device
510 * @tDQSD_max: Max W/R_n low to DQS/DQ driven by device
511 * @tDQSHZ_max: W/R_n high to DQS/DQ tri-state by device
512 * @tDQSQ_max: DQS-DQ skew, DQS to last DQ valid, per access
514 * @tDSC_min: DQS cycle time
/linux/drivers/memory/tegra/
H A Dtegra210-emc-cc-r21021.c100 int dqs = (dev); \
102 next->ptfv_list[dqs] = \
104 (next->ptfv_list[dqs] * \
109 __stringify(dev), nval, next->ptfv_list[dqs]); \
/linux/arch/arm64/boot/dts/freescale/
H A Dimx93-tqma9352.dtsi61 * no DQS, RXCLKSRC internal loop back, max 66 MHz
H A Dimx91-tqma9131.dtsi70 * no DQS, RXCLKSRC internal loop back, max 66 MHz
/linux/drivers/pinctrl/sunxi/
H A Dpinctrl-sun9i-a80.c242 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
253 SUNXI_FUNCTION(0x3, "nand0_b")), /* DQS */
H A Dpinctrl-sun8i-a33.c152 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
H A Dpinctrl-sun8i-h3.c230 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
H A Dpinctrl-sun8i-a23.c192 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
H A Dpinctrl-sun50i-h5.c235 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
H A Dpinctrl-sun8i-a83t.c170 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
H A Dpinctrl-sun50i-h6.c182 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
H A Dpinctrl-sun50i-h616.c170 SUNXI_FUNCTION(0x2, "nand0"), /* DQS */
/linux/arch/m68k/coldfire/
H A Dm53xx.c538 /* wait for DQS logic to relock */ in clock_pll()
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-colibri.dtsi632 gmi-dqs-pi2 {
H A Dtegra114-asus-tf701t.dts971 gmi-dqs-p {
/linux/arch/arm/boot/dts/rockchip/
H A Drk3128.dtsi1149 flash_dqs: flash-dqs {
/linux/drivers/net/ethernet/mellanox/mlxsw/
H A Dcmd.h1058 * SW should not post descriptors on nonoperational DQs.
/linux/arch/arm64/boot/dts/rockchip/
H A Dpx30.dtsi2083 flash_dqs: flash-dqs {
/linux/drivers/mtd/nand/raw/
H A Dcadence-nand-controller.c282 /* Register controls the DQS related timing. */
/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a77970.c1398 /* Octal-SPI flash: S#/CS, DQS */
H A Dpfc-r8a77980.c1692 /* Octal-SPI flash: S#/CS, DQS */

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