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/freebsd/sys/contrib/device-tree/Bindings/clock/ti/
H A Ddpll.txt1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 "ti,omap3-dpll-clock",
19 "ti,omap3-dpll-core-clock",
20 "ti,omap3-dpll-per-clock",
21 "ti,omap3-dpll-per-j-type-clock",
22 "ti,omap4-dpll-clock",
23 "ti,omap4-dpll-x2-clock",
24 "ti,omap4-dpll-core-clock",
[all …]
H A Dapll.txt11 a subtype of a DPLL [2], although a simplified one at that.
14 [2] Documentation/devicetree/bindings/clock/ti/dpll.txt
/freebsd/sys/arm/ti/clk/
H A Dti_dpll_clock.c54 * Documentation/devicetree/bindings/clock/ti/dpll.txt
92 { "ti,omap3-dpll-clock", TI_OMAP3_DPLL_CLOCK },
93 { "ti,omap3-dpll-core-clock", TI_OMAP3_DPLL_CORE_CLOCK },
94 { "ti,omap3-dpll-per-clock", TI_OMAP3_DPLL_PER_CLOCK },
95 { "ti,omap3-dpll-per-j-type-clock",TI_OMAP3_DPLL_PER_J_TYPE_CLOCK },
96 { "ti,omap4-dpll-clock", TI_OMAP4_DPLL_CLOCK },
97 { "ti,omap4-dpll-x2-clock", TI_OMAP4_DPLL_X2_CLOCK },
98 { "ti,omap4-dpll-core-clock", TI_OMAP4_DPLL_CORE_CLOCK },
99 { "ti,omap4-dpll-m4xen-clock", TI_OMAP4_DPLL_M4XEN_CLOCK },
100 { "ti,omap4-dpll-j-type-clock", TI_OMAP4_DPLL_J_TYPE_CLOCK },
[all …]
/freebsd/sys/contrib/device-tree/Bindings/media/i2c/
H A Dadv748x.yaml38 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
39 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
40 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
41 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
42 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
43 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
44 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
45 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
46 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
47 - enum: [ dpll, cp, hdmi, edid, repeater, infoframe, cbus, cec, sdp, txa, txb ]
[all …]
H A Dadv748x.txt28 "main", "dpll", "cp", "hdmi", "edid", "repeater",
70 reg-names = "main", "dpll", "cp", "hdmi", "edid", "repeater",
/freebsd/sys/contrib/device-tree/src/arm/ti/omap/
H A Ddra7xx-clocks.dtsi229 compatible = "ti,omap4-dpll-m4xen-clock";
235 dpll_abe_x2_ck: clock-dpll-abe-x2 {
237 compatible = "ti,omap4-dpll-x2-clock";
242 dpll_abe_m2x2_ck: clock-dpll-abe-m2x2-8@1f0 {
264 dpll_abe_m2_ck: clock-dpll-abe-m2-8@1f0 {
276 dpll_abe_m3x2_ck: clock-dpll-abe-m3x2-8@1f4 {
288 dpll_core_byp_mux: clock-dpll-core-byp-mux-23@12c {
299 compatible = "ti,omap4-dpll-core-clock";
305 dpll_core_x2_ck: clock-dpll-core-x2 {
307 compatible = "ti,omap4-dpll-x2-clock";
[all …]
H A Dam43xx-clocks.dtsi231 compatible = "ti,am3-dpll-core-clock";
237 dpll_core_x2_ck: clock-dpll-core-x2 {
239 compatible = "ti,am3-dpll-x2-clock";
244 dpll_core_m4_ck: clock-dpll-core-m4-8@2d38 {
256 dpll_core_m5_ck: clock-dpll-core-m5-8@2d3c {
268 dpll_core_m6_ck: clock-dpll-core-m6-8@2d40 {
282 compatible = "ti,am3-dpll-clock";
288 dpll_mpu_m2_ck: clock-dpll-mpu-m2-8@2d70 {
311 compatible = "ti,am3-dpll-clock";
317 dpll_ddr_m2_ck: clock-dpll-ddr-m2-8@2db0 {
[all …]
H A Dam33xx-clocks.dtsi190 compatible = "ti,am3-dpll-core-clock";
196 dpll_core_x2_ck: clock-dpll-core-x2 {
198 compatible = "ti,am3-dpll-x2-clock";
203 dpll_core_m4_ck: clock-dpll-core-m4@480 {
213 dpll_core_m5_ck: clock-dpll-core-m5@484 {
223 dpll_core_m6_ck: clock-dpll-core-m6@4d8 {
235 compatible = "ti,am3-dpll-clock";
241 dpll_mpu_m2_ck: clock-dpll-mpu-m2@4a8 {
253 compatible = "ti,am3-dpll-no-gate-clock";
259 dpll_ddr_m2_ck: clock-dpll-ddr-m2@4a0 {
[all …]
H A Domap54xx-clocks.dtsi119 compatible = "ti,omap4-dpll-m4xen-clock";
127 compatible = "ti,omap4-dpll-x2-clock";
201 compatible = "ti,omap4-dpll-core-clock";
209 compatible = "ti,omap4-dpll-x2-clock";
352 compatible = "ti,omap4-dpll-clock";
362 compatible = "ti,omap4-dpll-x2-clock";
402 compatible = "ti,omap5-mpu-dpll-clock";
586 compatible = "ti,omap4-dpll-clock";
594 compatible = "ti,omap4-dpll-x2-clock";
661 compatible = "ti,omap4-dpll-clock";
[all …]
H A Domap44xx-clocks.dtsi154 compatible = "ti,omap4-dpll-m4xen-clock";
162 compatible = "ti,omap4-dpll-x2-clock";
223 compatible = "ti,omap4-dpll-core-clock";
231 compatible = "ti,omap4-dpll-x2-clock";
390 compatible = "ti,omap4-dpll-clock";
400 compatible = "ti,omap4-dpll-x2-clock";
435 compatible = "ti,omap4-dpll-clock";
636 compatible = "ti,omap4-dpll-clock";
654 compatible = "ti,omap4-dpll-x2-clock";
748 compatible = "ti,omap4-dpll-j-type-clock";
H A Domap36xx-clocks.dtsi10 compatible = "ti,omap3-dpll-per-j-type-clock";
H A Domap36xx-am35xx-omap3430es2plus-clocks.dtsi27 compatible = "ti,omap3-dpll-clock";
H A Domap34xx-omap36xx-clocks.dtsi202 compatible = "ti,omap3-dpll-clock";
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dmicrochip,sparx5-dpll.yaml4 $id: http://devicetree.org/schemas/clock/microchip,sparx5-dpll.yaml#
7 title: Microchip Sparx5 DPLL Clock
13 The Sparx5 DPLL clock controller generates and supplies clock to
18 const: microchip,sparx5-dpll
46 compatible = "microchip,sparx5-dpll";
H A Dsprd,sc9863a-clk.yaml29 - sprd,sc9863a-dpll
/freebsd/sys/dev/ic/
H A Dz8530.h94 #define CMC_RC_DPLL 0x60 /* Rx Clock from DPLL. */
98 #define CMC_TC_DPLL 0x18 /* Tx Clock from DPLL */
103 #define CMC_TRXC_DPLL 0x03 /* -TRxC from DPLL */
180 #define MCB2_NRZI 0xe0 /* DPLL - NRZI mode. */
181 #define MCB2_FM 0xc0 /* DPLL - FM mode. */
182 #define MCB2_RTXC 0xa0 /* DPLL - Clock from -RTxC. */
183 #define MCB2_BRG 0x80 /* DPLL - Clock from BRG. */
184 #define MCB2_OFF 0x60 /* DPLL - Disable. */
185 #define MCB2_RMC 0x40 /* DPLL - Reset Missing Clock. */
186 #define MCB2_ESM 0x20 /* DPLL - Enter Search Mode. */
/freebsd/sys/contrib/device-tree/Bindings/phy/
H A Dti-phy.txt10 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
46 * "dpll_ref" - external dpll ref clk
47 * "dpll_ref_m2" - external dpll ref clk
/freebsd/sys/contrib/device-tree/src/arm64/sprd/
H A Dsharkl3.dtsi123 dpll: dpll { label
124 compatible = "sprd,sc9863a-dpll";
/freebsd/sys/contrib/device-tree/src/arm/samsung/
H A Dexynos5422-odroid-core.dtsi101 /* derived from 600MHz DPLL */
203 /* derived from 600MHz DPLL */
239 /* derived from 600MHz DPLL */
251 /* derived from 600MHz DPLL */
266 /* derived from 600MHz DPLL */
/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Dxlnx-zynqmp-clk.h15 #define DPLL 3 macro
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6q-dms-ba16.dts118 fsl,receive-dpll-mode = <1>;
/freebsd/contrib/llvm-project/clang/include/clang/Analysis/FlowSensitive/
H A DWatchedLiteralsSolver.h26 /// the Davis-Putnam-Logemann-Loveland (DPLL) algorithm [1], keeps references to
/freebsd/sys/dev/clk/rockchip/
H A Drk3328_cru.c254 GATE(0, "core_dpll_clk", "dpll", 0, 1),
648 PLIST(pll_src_apll_gpll_dpll_npll_p) = {"apll", "gpll", "dpll", "npll"};
682 static struct rk_clk_pll_def dpll = { variable
685 .name = "dpll",
833 .clk.pll = &dpll
H A Drk3399_cru.c63 GATE(0, "clk_core_l_dpll_src", "dpll", 0, 2),
74 GATE(0, "clk_core_b_dpll_src", "dpll", 1, 2),
99 GATE(0, "clk_ddrc_dpll_src", "dpll", 3, 2),
785 PLL(PLL_DPLL, "dpll", 0x40),
/freebsd/sys/arm/nvidia/tegra124/
H A Dtegra124_cpufreq.c458 /* XXX DPLL is not implemented yet */ in get_fdt_resources()
509 /* XXX DPLL is not implemented yet */ in tegra124_cpufreq_attach()

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