Lines Matching full:dpll

1 Binding for Texas Instruments DPLL clock.
6 register-mapped DPLL with usually two selectable input clocks
12 for the actual DPLL clock.
18 		"ti,omap3-dpll-clock",
19 		"ti,omap3-dpll-core-clock",
20 		"ti,omap3-dpll-per-clock",
21 		"ti,omap3-dpll-per-j-type-clock",
22 		"ti,omap4-dpll-clock",
23 		"ti,omap4-dpll-x2-clock",
24 		"ti,omap4-dpll-core-clock",
25 		"ti,omap4-dpll-m4xen-clock",
26 		"ti,omap4-dpll-j-type-clock",
27 		"ti,omap5-mpu-dpll-clock",
28 		"ti,am3-dpll-no-gate-clock",
29 		"ti,am3-dpll-j-type-clock",
30 		"ti,am3-dpll-no-gate-j-type-clock",
31 		"ti,am3-dpll-clock",
32 		"ti,am3-dpll-core-clock",
33 		"ti,am3-dpll-x2-clock",
34 		"ti,omap2-dpll-core-clock",
39 - reg : offsets for the register set for controlling the DPLL.
45 	"ssc-deltam" - DPLL supports spread spectrum clocking (SSC), contains
47 	"ssc-modfreq" - DPLL supports spread spectrum clocking (SSC), contains
50   ti,am3-* dpll types do not have autoidle register
51   ti,omap2-* dpll type does not support idlest / autoidle registers
54 - DPLL mode setting - defining any one or more of the following overrides
56 	- ti,low-power-stop : DPLL supports low power stop mode, gating output
57 	- ti,low-power-bypass : DPLL output matches rate of parent bypass clock
58 	- ti,lock : DPLL locks in programmed rate
59 	- ti,min-div : the minimum divisor to start from to round the DPLL
61 	- ti,ssc-deltam : DPLL supports spread spectrum clocking, frequency
63 	- ti,ssc-modfreq-hz : DPLL supports spread spectrum clocking, spread
65 	- ti,ssc-downspread : DPLL supports spread spectrum clocking, boolean
71 		compatible = "ti,omap4-dpll-core-clock";
78 		compatible = "ti,omap3-dpll-clock";
88 		compatible = "ti,am3-dpll-core-clock";
95 		compatible = "ti,omap2-dpll-core-clock";
102 		compatible = "ti,am3-dpll-no-gate-clock";