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/linux/drivers/clk/tegra/
H A Dclk-dfll.c3 * clk-dfll.c - Tegra DFLL clock source common code
10 * This library is for the DVCO and DFLL IP blocks on the Tegra124
13 * collectively as the "DFLL."
15 * The DFLL is a root clocksource which tolerates some amount of
18 * DFLL can be operated in either open-loop mode or closed-loop mode.
19 * In open-loop mode, the DFLL generates an output clock appropriate
21 * target frequency, the DFLL minimizes supply voltage while
24 * Devices clocked by the DFLL must be able to tolerate frequency
49 #include "clk-dfll.h"
53 * DFLL control registers - access via dfll_{readl,writel}
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H A Dclk-dfll.h3 * clk-dfll.h - prototypes and macros for the Tegra DFLL clocksource driver
20 * struct tegra_dfll_soc_data - SoC-specific hooks/integration for the DFLL driver
21 * @dev: struct device * that holds the OPP table for the DFLL
H A DMakefile5 obj-y += clk-dfll.o
25 obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o
H A Dclk-tegra124-dfll-fcpu.c3 * Tegra124 DFLL FCPU clock source driver
21 #include "clk-dfll.h"
613 .compatible = "nvidia,tegra114-dfll",
617 .compatible = "nvidia,tegra124-dfll",
621 .compatible = "nvidia,tegra210-dfll",
744 .name = "tegra124-dfll",
H A Dclk-tegra124.c1384 * tegra124_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
1386 * Assert the reset line of the DFLL's DVCO. No return value.
1399 * tegra124_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
1401 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
H A Dclk-tegra210.c3634 * tegra210_clock_assert_dfll_dvco_reset - assert the DFLL's DVCO reset
3636 * Assert the reset line of the DFLL's DVCO. No return value.
3649 * tegra210_clock_deassert_dfll_dvco_reset - deassert the DFLL's DVCO reset
3651 * Deassert the reset line of the DFLL's DVCO, allowing the DVCO to
/linux/drivers/cpufreq/
H A Dtegra124-cpufreq.c79 priv->dfll_clk = of_clk_get_by_name(np, "dfll"); in tegra124_cpufreq_probe()
131 * to PLLP and disable DFLL. in tegra124_cpufreq_suspend()
151 * Enable DFLL clock and switch CPU clock source back to DFLL. in tegra124_cpufreq_resume()
155 dev_err(dev, "failed to enable DFLL clock for CPU: %d\n", err); in tegra124_cpufreq_resume()
161 dev_err(dev, "failed to reparent to DFLL clock: %d\n", err); in tegra124_cpufreq_resume()
213 * the regulator and the DFLL clock in tegra_cpufreq_init()
/linux/Documentation/devicetree/bindings/cpufreq/
H A Dnvidia,tegra124-cpufreq.txt14 - dfll: Fast DFLL clocksource that also automatically scales CPU voltage.
34 <&dfll>;
35 clock-names = "cpu_g", "pll_x", "pll_p", "dfll";
/linux/drivers/gpu/drm/amd/pm/swsmu/inc/pmfw_if/
H A Dsmu11_driver_if_sienna_cichlid.h452 //Piecewise linear droop model, Sienna_Cichlid currently used only for GFX DFLL
713 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
913 // GFXCLK DFLL Spread Spectrum
1073 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
1274 // GFXCLK DFLL Spread Spectrum
H A Dsmu11_driver_if_navi10.h614 uint8_t GfxclkSource; // 0 = PLL, 1 = DFLL
785 // GFXCLK DFLL Spread Spectrum
H A Dsmu13_driver_if_aldebaran.h335 uint8_t GfxclkSource; // GfxclkSrc_e [0 = PLL, 1 = DFLL]
H A Dsmu14_driver_if_v14_0.h1178 // DFLL
1476 // DFLL Spread Spectrum
/linux/arch/arm/boot/dts/nvidia/
H A Dtegra124.dtsi1045 dfll: clock@70110000 { label
1046 compatible = "nvidia,tegra124-dfll";
1047 reg = <0 0x70110000 0 0x100>, /* DFLL control */
1303 <&dfll>;
1304 clock-names = "cpu_g", "cpu_lp", "pll_x", "pll_p", "dfll";
H A Dtegra124-jetson-tk1.dts1836 /* CPU DFLL clock */
H A Dtegra124-apalis-v1.2.dtsi1954 /* CPU DFLL clock */
H A Dtegra124-apalis.dtsi1946 /* CPU DFLL clock */
H A Dtegra124-xiaomi-mocha.dts2438 /* CPU DFLL clock */
/linux/sound/soc/codecs/
H A Drt715-sdca.c1052 /* DFLL Calibration trigger */ in rt715_sdca_io_init()