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/freebsd/sys/contrib/device-tree/include/dt-bindings/clock/
H A Drk3399-ddr.h7 * DDR3 SDRAM Standard Speed Bins include tCK, tRCD, tRP, tRAS and tRC for
11 /* DDR3-800 (5-5-5) */
13 /* DDR3-800 (6-6-6) */
15 /* DDR3-1066 (6-6-6) */
17 /* DDR3-1066 (7-7-7) */
19 /* DDR3-1066 (8-8-8) */
21 /* DDR3-1333 (7-7-7) */
23 /* DDR3-1333 (8-8-8) */
25 /* DDR3-1333 (9-9-9) */
27 /* DDR3-1333 (10-10-10) */
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/freebsd/sys/contrib/device-tree/Bindings/devfreq/
H A Drk3399_dmc.txt29 it selects the DDR3 cl-trp-trcd type. It must be
30 set according to "Speed Bin" in DDR3 datasheet,
32 for the DDR3 being used.
64 - rockchip,dram_dll_dis_freq : Defines the DDR3 DLL bypass frequency in MHz.
66 DDR3 DLL will be bypassed. Note: if DLL was bypassed,
74 - rockchip,ddr3_odt_dis_freq : When the DRAM type is DDR3, this parameter defines
80 - rockchip,ddr3_drv : When the DRAM type is DDR3, this parameter defines
84 - rockchip,ddr3_odt : When the DRAM type is DDR3, this parameter defines
88 - rockchip,phy_ddr3_ca_drv : When the DRAM type is DDR3, this parameter defines
93 - rockchip,phy_ddr3_dq_drv : When the DRAM type is DDR3, this parameter defines
[all …]
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/
H A Drockchip,rk3399-dmc.yaml52 DDR3 cl-trp-trcd type. It must be set according to "Speed Bin" in DDR3
53 datasheet; DO NOT use a smaller "Speed Bin" than specified for the DDR3
108 Defines the DDR3 DLL bypass frequency in MHz. When DDR frequency is less
109 than DRAM_DLL_DISB_FREQ, DDR3 DLL will be bypassed.
130 When the DRAM type is DDR3, this parameter defines the ODT disable
138 When the DRAM type is DDR3, this parameter defines the DRAM side drive
146 When the DRAM type is DDR3, this parameter defines the DRAM side ODT
154 When the DRAM type is DDR3, this parameter defines the phy side CA line
162 When the DRAM type is DDR3, thi
[all...]
H A Drenesas,dbsc.yaml15 different names, e.g. "DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
H A Dnvidia,tegra30-emc.yaml19 LPDDR3, and DDR3.
/freebsd/sys/dev/jedec_dimm/
H A Djedec_dimm.h35 * At a minimum, they have an EEPROM containing either 256 bytes (DDR3) or 512
40 * JEDEC Standard 21-C, Annex K (DDR3)
49 * JEDEC Standard 21-C, TSE2002av (DDR3)
78 /* The offsets and lengths of various SPD bytes are defined in Annex K (DDR3)
135 * between TSE2002av (DDR3) and TSE2004av (DDR4).
H A Djedec_dimm.c61 char part_str[21]; /* 18 (DDR3) or 20 (DDR4) chars, plus terminator */
300 (void) snprintf(sc->type_str, sizeof(sc->type_str), "DDR3"); in jedec_dimm_attach()
352 * is in fact present. (While DDR3 and DDR4 don't explicitly require a in jedec_dimm_attach()
353 * TSOD, essentially all DDR3 and DDR4 DIMMs include one.) But, as in jedec_dimm_attach()
462 * Calculate the capacity of a DIMM. Both DDR3 and DDR4 encode "geometry"
465 * most of them. Unless otherwise noted, the same formulas apply for both DDR3
635 * both DDR3 and DDR4. in jedec_dimm_capacity()
870 * Both DDR3 and DDR4 encode manufacturing date as a one-byte BCD-encoded
1017 /* This driver currently only supports DDR3 and DDR4 SPDs. */ in jedec_dimm_probe()
1022 device_set_desc(dev, "DDR3 DIMM"); in jedec_dimm_probe()
/freebsd/share/man/man4/
H A Djedec_dimm.432 .Nd report asset information and temperatures for JEDEC DDR3 / DDR4 DIMMs
58 (SPD) data on JEDEC DDR3 and DDR4 DIMMs.
90 the DIMM type (DDR3 or DDR4)
/freebsd/sys/contrib/device-tree/src/arm64/marvell/
H A Darmada-3720-db.dts4 * (DB-88F3720-DDR3)
20 model = "Marvell Armada 3720 Development Board DB-88F3720-DDR3";
H A Darmada-3720-uDPU.dtsi4 * Based on Marvell Armada 3720 development board (DB-88F3720-DDR3)
/freebsd/sys/contrib/device-tree/Bindings/clock/
H A Dti-keystone-pllctrl.txt4 and a majority of the peripheral clocks (all but the ARM CorePacs, DDR3 and
/freebsd/sys/contrib/device-tree/Bindings/edac/
H A Daspeed-sdram-edac.txt3 The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error
/freebsd/sys/contrib/device-tree/Bindings/arm/bcm/
H A Dbrcm,hr2.yaml12 A9 ARM CPUs, DDR2/DDR3 memory, PCIe GEN-2, USB 2.0 and USB 3.0, serial and NAND
H A Dbrcm,nsp.yaml14 DDR3 memory, PCIE Gen-2, USB 2.0 and USB 3.0, serial and NAND flash,
/freebsd/sys/contrib/device-tree/Bindings/regulator/
H A Drenesas,raa215300.yaml14 32-bit and 64-bit MCU and MPU applications. It supports DDR3, DDR3L, DDR4,
/freebsd/sys/contrib/device-tree/Bindings/memory-controllers/ti/
H A Demif.txt5 DDR2/DDR3/LPDDR2 protocols. This binding describes a given instance
/freebsd/sys/contrib/device-tree/src/powerpc/
H A Dturris1x.dts60 /* DDR3 SPD/EEPROM PSWP instruction */
88 /* DDR3 SPD/EEPROM */
/freebsd/sys/contrib/device-tree/src/arm/marvell/
H A Darmada-370-db.dts4 * (DB-88F6710-BP-DDR3)
/freebsd/sys/contrib/device-tree/src/powerpc/fsl/
H A Dkmcent2.dts133 label = "ddr3-spd";
/freebsd/sys/contrib/device-tree/src/arm/nxp/imx/
H A Dimx6ull-dhcor-som.dtsi118 * backward compatibility to only 1.5V DDR3 memory,
/freebsd/sys/contrib/device-tree/src/arm64/allwinner/
H A Dsun50i-a64-teres-i.dts274 regulator-name = "vcc-ddr3";
H A Dsun50i-a64-olinuxino.dts267 regulator-name = "vcc-ddr3";
/freebsd/sys/contrib/device-tree/src/arm64/amlogic/
H A Dmeson-gxbb-odroidc2.dts151 ddr3_1v5: regulator-ddr3-1v5 {
/freebsd/sys/contrib/device-tree/src/arm/amlogic/
H A Dmeson8b-ec100.dts212 vcc_ddr3: regulator-vcc-ddr3 {
/freebsd/sys/contrib/device-tree/src/arm/ti/keystone/
H A Dkeystone-clocks.dtsi276 clock-output-names = "ddr3-0";

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